AArch64: Add pattern for unsigned widenings (uxtl) to zip{1,2}

This changes unpack instructions to use zip{1,2} when doing a zero-extending
widening operation.  Permutes generally have a higher throughput than the
widening operations. Zeros are shuffled into the top half of the registers.

The testcase

void d2 (unsigned * restrict a, unsigned short *b, int n)
{
    for (int i = 0; i < (n & -8); i++)
      a[i] = b[i];
}

now generates:

        movi    v1.4s, 0
.L3:
        ldr     q0, [x1], 16
        zip1    v2.8h, v0.8h, v1.8h
        zip2    v0.8h, v0.8h, v1.8h
        stp     q2, q0, [x0]
        add     x0, x0, 32
        cmp     x1, x2
        bne     .L3

instead of:

.L3:
        ldr     q0, [x1], 16
        uxtl    v1.4s, v0.4h
        uxtl2   v0.4s, v0.8h
        stp     q1, q0, [x0]
        add     x0, x0, 32
        cmp     x1, x2
        bne     .L3

Since we need the extra 0 register we do this only for the vectorizer's lo/hi
pairs when we know the 0 will be floated outside of the loop.

This gives an 8% speed-up in Imagick in SPECCPU 2017 on Neoverse V2.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (vec_unpack<su>_lo_<mode,
	vec_unpack<su>_lo_<mode): Split into...
	(vec_unpacku_lo_<mode, vec_unpacks_lo_<mode,
	vec_unpacku_lo_<mode, vec_unpacks_lo_<mode): ...These.
	(aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
	(aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
	* config/aarch64/iterators.md (PERM_EXTEND, perm_index): New.
	(perm_hilo): Add UNSPEC_ZIP1, UNSPEC_ZIP2.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/simd/vmovl_high_1.c: Update codegen.
	* gcc.target/aarch64/uxtl-combine-1.c: New test.
	* gcc.target/aarch64/uxtl-combine-2.c: New test.
	* gcc.target/aarch64/uxtl-combine-3.c: New test.
	* gcc.target/aarch64/uxtl-combine-4.c: New test.
	* gcc.target/aarch64/uxtl-combine-5.c: New test.
	* gcc.target/aarch64/uxtl-combine-6.c: New test.

0 files changed, 0 insertions, 0 deletions