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author | ShiYulong <shiyulong@iscas.ac.cn> | 2022-05-10 11:25:25 +0800 |
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committer | Kito Cheng <kito.cheng@sifive.com> | 2022-05-24 21:00:39 +0800 |
commit | 3df3ca9014f94fe4af07444fea19b4ab29ba8e73 (patch) | |
tree | 5e893fc3dd82f628ba514e0e668c82fa9f3bb09b /gcc/d/expr.cc | |
parent | 23c738bcba78a9df2259dd0626669c9a0aa04d1e (diff) | |
download | gcc-3df3ca9014f94fe4af07444fea19b4ab29ba8e73.zip gcc-3df3ca9014f94fe4af07444fea19b4ab29ba8e73.tar.gz gcc-3df3ca9014f94fe4af07444fea19b4ab29ba8e73.tar.bz2 |
RISC-V: Cache Management Operation instructions
This commit adds cbo.clea, cbo.flush, cbo.inval, cbo.zero, prefetch.i,
prefetch.r and prefetch.w instructions.
diff with the previous version:
We use unspec_volatile instead of unspec for those cache operations.
We use UNSPECV instead of UNSPEC and move them to unspecv.
gcc/ChangeLog:
* config/riscv/predicates.md (imm5_operand): Add a new operand type for
prefetch instructions.
* config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA
Extensions.
(RISCV_ATYPE_SI): New.
(RISCV_ATYPE_DI): New.
* config/riscv/riscv-ftypes.def (0): New.
(1): New.
* config/riscv/riscv.md (riscv_clean_<mode>): New.
(riscv_flush_<mode>): New.
(riscv_inval_<mode>): New.
(riscv_zero_<mode>): New.
(prefetch): New.
(riscv_prefetchi_<mode>): New.
* config/riscv/riscv-cmo.def: New file.
Diffstat (limited to 'gcc/d/expr.cc')
0 files changed, 0 insertions, 0 deletions