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| author | liuhongt <hongtao.liu@intel.com> | 2022-03-28 11:12:37 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-03-28 16:14:37 +0800 |
| commit | e4352a0fee49441a32d12e8d8b98c425cfed4a86 (patch) | |
| tree | 9b1a031788c7843ad96143e09d39e60603956d04 /gcc/ctfout.cc | |
| parent | 50f9148f7a8daf1fa1608cb23595c3cca191da0f (diff) | |
| download | gcc-e4352a0fee49441a32d12e8d8b98c425cfed4a86.zip gcc-e4352a0fee49441a32d12e8d8b98c425cfed4a86.tar.gz gcc-e4352a0fee49441a32d12e8d8b98c425cfed4a86.tar.bz2 | |
Fix typo in vec_setv8hi_0.
pinsrw is available for both reg and mem operand under sse2.
pextrw requires sse4.1 for mem operands.
The patch change attr "isa" for pinsrw mem alternative from sse4_noavx
to noavx, will enable below optimization.
- movzwl (%rdi), %eax
pxor %xmm1, %xmm1
- pinsrw $0, %eax, %xmm1
+ pinsrw $0, (%rdi), %xmm1
movdqa %xmm1, %xmm0
gcc/ChangeLog:
PR target/105066
* config/i386/sse.md (vec_set<mode>_0): Change attr "isa" of
alternative 4 from sse4_noavx to noavx.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr105066.c: New test.
Diffstat (limited to 'gcc/ctfout.cc')
0 files changed, 0 insertions, 0 deletions