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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2013-09-27 19:33:52 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2013-09-27 19:33:52 +0000 |
| commit | 19cdb489dac2ec2967532b524c904dc9dce4ea88 (patch) | |
| tree | 57bd4201f7f23a7459b159408dd7f0545ef4f526 /gcc/cppdefault.h | |
| parent | 8bcd5487e589c17afc77c982589247b106caba73 (diff) | |
| download | gcc-19cdb489dac2ec2967532b524c904dc9dce4ea88.zip gcc-19cdb489dac2ec2967532b524c904dc9dce4ea88.tar.gz gcc-19cdb489dac2ec2967532b524c904dc9dce4ea88.tar.bz2 | |
rs6000.c (rs6000_hard_regno_mode_ok): Allow DFmode...
[gcc]
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
DFmode, DImode, and SFmode in the upper VSX registers based on the
-mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS
if -mpower8-vector. Combine -mvsx-timode handling with the rest
of the VSX register handling.
* config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.
(f32_sv): Likewise.
(zero_extendsidi2_lfiwzx): Add support for loading into the
Altivec registers with -mpower8-vector. Use wu/wv constraints to
only do VSX memory options on Altivec registers.
(extendsidi2_lfiwax): Likewise.
(extendsfdf2_fpr): Likewise.
(mov<mode>_hardfloat, SF/SD modes): Likewise.
(mov<mode>_hardfloat32, DF/DD modes): Likewise.
(mov<mode>_hardfloat64, DF/DD modes): Likewise.
(movdi_internal64): Likewise.
[gcc/testsuite]
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf
and -mupper-regs-df.
From-SVN: r202984
Diffstat (limited to 'gcc/cppdefault.h')
0 files changed, 0 insertions, 0 deletions