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authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>2022-12-20 22:56:49 +0800
committerKito Cheng <kito.cheng@sifive.com>2022-12-23 13:41:23 +0800
commitb47b33c799bd4874a4c81fb71708ff1c3dd150ff (patch)
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parent37fd10fd3eb42ea4487d93521a267ba08a9f8575 (diff)
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RISC-V: Remove side effects of vsetvl pattern in RTL.
gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects. * config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern.
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