AArch64: Add pattern for sshr to cmlt

This optimizes signed right shift by BITSIZE-1 into a cmlt operation which is
more optimal because generally compares have a higher throughput than shifts.

On AArch64 the result of the shift would have been either -1 or 0 which is the
results of the compare.

i.e.

void e (int * restrict a, int *b, int n)
{
    for (int i = 0; i < n; i++)
      b[i] = a[i] >> 31;
}

now generates:

.L4:
        ldr     q0, [x0, x3]
        cmlt    v0.4s, v0.4s, #0
        str     q0, [x1, x3]
        add     x3, x3, 16
        cmp     x4, x3
        bne     .L4

instead of:

.L4:
        ldr     q0, [x0, x3]
        sshr    v0.4s, v0.4s, 31
        str     q0, [x1, x3]
        add     x3, x3, 16
        cmp     x4, x3
        bne     .L4

Thanks,
Tamar

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_simd_ashr<mode>): Add case cmp
	case.
	* config/aarch64/constraints.md (D1): New.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/shl-combine-2.c: New test.
	* gcc.target/aarch64/shl-combine-3.c: New test.
	* gcc.target/aarch64/shl-combine-4.c: New test.
	* gcc.target/aarch64/shl-combine-5.c: New test.

0 files changed, 0 insertions, 0 deletions