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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-15 15:15:08 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-15 15:40:59 +0800 |
| commit | d85161a73b9bdd382e62ca1ba3f9f962971a9695 (patch) | |
| tree | 1fe63f68c7be565660430e39f747cbb606f45aa7 /gcc/cp/tree.cc | |
| parent | 5f580e24088b85be95aeae0ceb2edff0cea861dd (diff) | |
| download | gcc-d85161a73b9bdd382e62ca1ba3f9f962971a9695.zip gcc-d85161a73b9bdd382e62ca1ba3f9f962971a9695.tar.gz gcc-d85161a73b9bdd382e62ca1ba3f9f962971a9695.tar.bz2 | |
RISC-V: Disallow RVV mode address for any load/store[PR112535]
This patch is quite obvious patch which disallow for load/store address register
with RVV mode.
PR target/112535
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV modes base address.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112535.c: New test.
Diffstat (limited to 'gcc/cp/tree.cc')
0 files changed, 0 insertions, 0 deletions