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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2021-11-14 22:56:11 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-14 19:49:22 +0100 |
| commit | b4fca4fc70dc76cf18406fd2b046c834d976aa90 (patch) | |
| tree | 67e8e1beeb95f3bf171e7fe86579bfbea93ecd22 /gcc/cp/tree.cc | |
| parent | d758d1908899cf388638e1c1790c6f10e7441090 (diff) | |
| download | gcc-b4fca4fc70dc76cf18406fd2b046c834d976aa90.zip gcc-b4fca4fc70dc76cf18406fd2b046c834d976aa90.tar.gz gcc-b4fca4fc70dc76cf18406fd2b046c834d976aa90.tar.bz2 | |
RISC-V: Add basic support for the Ventana-VT1 core
The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and
XVentanaCondOps.
This introduces a placeholder -mcpu=ventana-vt1, so tooling and
scripts don't need to change once full support (pipeline, tuning,
etc.) will become public later.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1.
(RISCV_CORE): Ditto.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto.
* config/riscv/riscv.cc: Add tune_info for ventana-vt1.
* doc/invoke.texi: Document -mcpu= and -mtune with ventana-vt1.
Diffstat (limited to 'gcc/cp/tree.cc')
0 files changed, 0 insertions, 0 deletions