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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-04-19 18:41:51 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-04-20 21:21:03 +0800 |
| commit | a2d12abedc89a9439fd6aadc38730fdadca0684f (patch) | |
| tree | a1bf575970880c6c0210029df116d99a3bf28921 /gcc/cp/tree.cc | |
| parent | 98ebdda3fd81c2c87ef0e73de9c94135fb49210f (diff) | |
| download | gcc-a2d12abedc89a9439fd6aadc38730fdadca0684f.zip gcc-a2d12abedc89a9439fd6aadc38730fdadca0684f.tar.gz gcc-a2d12abedc89a9439fd6aadc38730fdadca0684f.tar.bz2 | |
RISC-V: Fix wrong check of register occurrences [PR109535]
count_occurrences will conly count same RTX (same code and same mode),
but what we want to track is the occurrence of a register, a register
might appeared in the insn with different mode or contain in SUBREG.
Testcase coming from Kito.
gcc/ChangeLog:
PR target/109535
* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
(pass_vsetvl::cleanup_insns): Fix bug.
gcc/testsuite/ChangeLog:
PR target/109535
* g++.target/riscv/rvv/base/pr109535.C: New test.
* gcc.target/riscv/rvv/base/pr109535.c: New test.
Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>
Diffstat (limited to 'gcc/cp/tree.cc')
0 files changed, 0 insertions, 0 deletions