RISC-V: Fix incorrect LCM delete bug [VSETVL PASS]

This patch fixes the recent noticed bug in RV32 glibc.

We incorrectly deleted a vsetvl:

        ...
	and	a4,a4,a3
	vmv.v.i	v1,0                 ---> Missed vsetvl cause illegal instruction report.
	vse8.v	v1,0(a5)

The root cause the laterin in LCM is incorrect.

      BB 358:
        avloc: n_bits = 2, set = {}
        kill: n_bits = 2, set = {}
        antloc: n_bits = 2, set = {}
        transp: n_bits = 2, set = {}
        avin: n_bits = 2, set = {}
        avout: n_bits = 2, set = {}
        del: n_bits = 2, set = {}

cause LCM let BB 360 delete the vsetvl:

      BB 360:
        avloc: n_bits = 2, set = {}
        kill: n_bits = 2, set = {}
        antloc: n_bits = 2, set = {}
        transp: n_bits = 2, set = {0 1 }
        avin: n_bits = 2, set = {}
        avout: n_bits = 2, set = {}
        del: n_bits = 2, set = {1}

Also, remove unknown vsetvl info into local computation since it is unnecessary.

Tested on both RV32/RV64 no regression.

	PR target/113469

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr113469.c: New test.

0 files changed, 0 insertions, 0 deletions