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| author | Tamar Christina <tamar.christina@arm.com> | 2024-07-05 12:09:21 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-07-05 12:09:21 +0100 |
| commit | 6ff698106644af39da9e0eda51974fdcd111280d (patch) | |
| tree | 2f96b1146f9f1369f812dfa56565e4d4a73c0d8d /gcc/cp/module.cc | |
| parent | ae07f62a70ee2d0fdd7d8786122ae6360cfd4ca9 (diff) | |
| download | gcc-6ff698106644af39da9e0eda51974fdcd111280d.zip gcc-6ff698106644af39da9e0eda51974fdcd111280d.tar.gz gcc-6ff698106644af39da9e0eda51974fdcd111280d.tar.bz2 | |
AArch64: remove aarch64_simd_vec_unpack<su>_lo_
The fix for PR18127 reworked the uxtl to zip optimization.
In doing so it undid the changes in aarch64_simd_vec_unpack<su>_lo_ and this now
no longer matches aarch64_simd_vec_unpack<su>_hi_. It still works because the
RTL generated by aarch64_simd_vec_unpack<su>_lo_ overlaps with the general zero
extend RTL and so because that one is listed before the lo pattern recog picks
it instead.
This removes aarch64_simd_vec_unpack<su>_lo_.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(aarch64_simd_vec_unpack<su>_lo_<mode>): Remove.
(vec_unpack<su>_lo_<mode): Simplify.
* config/aarch64/aarch64.cc (aarch64_gen_shareable_zero): Update
comment.
Diffstat (limited to 'gcc/cp/module.cc')
0 files changed, 0 insertions, 0 deletions