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| author | Patrick O'Neill <patrick@rivosinc.com> | 2024-06-10 17:00:38 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2024-06-12 11:19:13 -0700 |
| commit | 439c0cc9f7f6e83b898cabbd2e34f98484b432d3 (patch) | |
| tree | 8f6965c50182f42e6804c7b110daf50a7374f237 /gcc/cp/module.cc | |
| parent | 6343adcef7de1a1214c9b6dd845810aa4a0d19e5 (diff) | |
| download | gcc-439c0cc9f7f6e83b898cabbd2e34f98484b432d3.zip gcc-439c0cc9f7f6e83b898cabbd2e34f98484b432d3.tar.gz gcc-439c0cc9f7f6e83b898cabbd2e34f98484b432d3.tar.bz2 | |
RISC-V: Allow any temp register to be used in amo tests
We artifically restrict the temp registers to be a[0-9]+ when other
registers like t[0-9]+ are valid too. Update to make the regex
accept any register for the temp value.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register regex.
* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Diffstat (limited to 'gcc/cp/module.cc')
0 files changed, 0 insertions, 0 deletions