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| author | liuhongt <hongtao.liu@intel.com> | 2022-10-27 18:48:41 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-11-01 11:23:45 +0800 |
| commit | 5c5ef2f9ab545b680cd4bb6c540a9dadb12ead86 (patch) | |
| tree | 500d8816c1ea6a7fb678cbdd9748468220e0f655 /gcc/cp/lambda.cc | |
| parent | af6d747df7e311a6555dda3a75f6724ecc4481bd (diff) | |
| download | gcc-5c5ef2f9ab545b680cd4bb6c540a9dadb12ead86.zip gcc-5c5ef2f9ab545b680cd4bb6c540a9dadb12ead86.tar.gz gcc-5c5ef2f9ab545b680cd4bb6c540a9dadb12ead86.tar.bz2 | |
Enable more optimization for 32-bit/64-bit shrd/shld with imm shift count.
This patch doens't handle variable count since it require 5 insns to
be combined to get wanted pattern, but current pass_combine only
supports at most 4.
This patch doesn't handle 16-bit shrd/shld either.
gcc/ChangeLog:
PR target/55583
* config/i386/i386.md (*x86_64_shld_1): Rename to ..
(x86_64_shld_1): .. this.
(*x86_shld_1): Rename to ..
(x86_shld_1): .. this.
(*x86_64_shrd_1): Rename to ..
(x86_64_shrd_1): .. this.
(*x86_shrd_1): Rename to ..
(x86_shrd_1): .. this.
(*x86_64_shld_shrd_1_nozext): New pre_reload splitter.
(*x86_shld_shrd_1_nozext): Ditto.
(*x86_64_shrd_shld_1_nozext): Ditto.
(*x86_shrd_shld_1_nozext): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr55583.c: New test.
Diffstat (limited to 'gcc/cp/lambda.cc')
0 files changed, 0 insertions, 0 deletions