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| author | Jakub Jelinek <jakub@gcc.gnu.org> | 2013-10-30 18:59:44 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2013-10-30 18:59:44 +0100 |
| commit | 1079f7a198ba7e1114d8dce44f72a00cf9abb8eb (patch) | |
| tree | 2cf379154dd0a87b9e80401eb835d6d1776b4529 /gcc/cp/cp-array-notation.c | |
| parent | 3e4403a4c4affc7ba55f69136e74c25a0a74d84e (diff) | |
| download | gcc-1079f7a198ba7e1114d8dce44f72a00cf9abb8eb.zip gcc-1079f7a198ba7e1114d8dce44f72a00cf9abb8eb.tar.gz gcc-1079f7a198ba7e1114d8dce44f72a00cf9abb8eb.tar.bz2 | |
re PR target/47754 ([missed optimization] AVX allows unaligned memory operands but GCC uses unaligned load and register operand)
PR target/47754
* config/i386/i386.c (ix86_avx256_split_vector_move_misalign): If
op1 is misaligned_operand, just use *mov<mode>_internal insn
rather than UNSPEC_LOADU load.
(ix86_expand_vector_move_misalign): Likewise (for TARGET_AVX only).
Avoid gen_lowpart on op0 if it isn't MEM.
* gcc.target/i386/avx256-unaligned-load-1.c: Adjust scan-assembler
and scan-assembler-not regexps.
* gcc.target/i386/avx256-unaligned-load-2.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-3.c: Likewise.
* gcc.target/i386/avx256-unaligned-load-4.c: Likewise.
* gcc.target/i386/l_fma_float_1.c: Use pattern for
scan-assembler-times instead of just one insn name.
* gcc.target/i386/l_fma_float_2.c: Likewise.
* gcc.target/i386/l_fma_float_3.c: Likewise.
* gcc.target/i386/l_fma_float_4.c: Likewise.
* gcc.target/i386/l_fma_float_5.c: Likewise.
* gcc.target/i386/l_fma_float_6.c: Likewise.
* gcc.target/i386/l_fma_double_1.c: Likewise.
* gcc.target/i386/l_fma_double_2.c: Likewise.
* gcc.target/i386/l_fma_double_3.c: Likewise.
* gcc.target/i386/l_fma_double_4.c: Likewise.
* gcc.target/i386/l_fma_double_5.c: Likewise.
* gcc.target/i386/l_fma_double_6.c: Likewise.
From-SVN: r204219
Diffstat (limited to 'gcc/cp/cp-array-notation.c')
0 files changed, 0 insertions, 0 deletions