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| author | Christophe Lyon <christophe.lyon@arm.com> | 2022-09-29 15:34:11 +0200 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@arm.com> | 2022-09-30 13:55:50 +0200 |
| commit | c09663eabfb84ac56ddd8d44abcab3f4902c83bd (patch) | |
| tree | 23c95576f705a5d5bfecc0ff85c6b242408e603d /gcc/cp/constraint.cc | |
| parent | 44510e44e717d9c05b0c5d197a73676a9427e32f (diff) | |
| download | gcc-c09663eabfb84ac56ddd8d44abcab3f4902c83bd.zip gcc-c09663eabfb84ac56ddd8d44abcab3f4902c83bd.tar.gz gcc-c09663eabfb84ac56ddd8d44abcab3f4902c83bd.tar.bz2 | |
testsuite: [arm] Relax expected register names in MVE tests
These two tests have hardcoded q0 as destination/source of load/store
instructions, but this register is actually used only under
-mfloat-abi=hard. When using -mfloat-abi=softfp, other registers
(eg. q3) can be used to transfer function arguments from core
registers to MVE registers, making the expected regexp fail.
This small patch replaces q0 with q[0-7] to accept any 'q' register.
In several places where we had q[0-9]+, replace it with q[0-7] as MVE
only has q0-q7 registers.
OK for trunk?
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/mve_load_memory_modes.c: Update expected
registers.
* gcc.target/arm/mve/mve_store_memory_modes.c: Likewise.
Diffstat (limited to 'gcc/cp/constraint.cc')
0 files changed, 0 insertions, 0 deletions