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| author | Kito Cheng <kito.cheng@sifive.com> | 2020-03-11 17:48:10 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2020-03-12 00:57:19 +0800 |
| commit | 5fea87cc7902c7c03c0d3c8cf7784cd99db8315d (patch) | |
| tree | 57fd1d3b69a148a205eeb4a8a838492e9b36547f /gcc/cp/constraint.cc | |
| parent | cb99630f254aaec6591e0a200b79905b31d24eb3 (diff) | |
| download | gcc-5fea87cc7902c7c03c0d3c8cf7784cd99db8315d.zip gcc-5fea87cc7902c7c03c0d3c8cf7784cd99db8315d.tar.gz gcc-5fea87cc7902c7c03c0d3c8cf7784cd99db8315d.tar.bz2 | |
RISC-V: Fix testsuite regression due to recent IRA changes.
After IRA changes, atomic version will use one more register, but
non-atomic still use 2 registers, however this testcase isn't testing for
atomic feature, so I decide change the testcase to always use COUNT++
to test.
ChangeLog
gcc/testsuite/
Kito Cheng <kito.cheng@sifive.com>
* gcc.target/riscv/interrupt-2.c: Update testcase and expected output.
Diffstat (limited to 'gcc/cp/constraint.cc')
0 files changed, 0 insertions, 0 deletions