rs6000: Load high and low part of 64bit constant independently

Compare with previous version, this patch updates the comments only.
https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html

For a complicate 64bit constant, below is one instruction-sequence to
build:
	lis 9,0x800a
	ori 9,9,0xabcd
	sldi 9,9,32
	oris 9,9,0xc167
	ori 9,9,0xfa16

while we can also use below sequence to build:
	lis 9,0xc167
	lis 10,0x800a
	ori 9,9,0xfa16
	ori 10,10,0xabcd
	rldimi 9,10,32,0
This sequence is using 2 registers to build high and low part firstly,
and then merge them.

In parallel aspect, this sequence would be faster. (Ofcause, using 1 more
register with potential register pressure).

The instruction sequence with two registers for parallel version can be
generated only if can_create_pseudo_p.  Otherwise, the one register
sequence is generated.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
	more parallel code if can_create_pseudo_p.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/parall_5insn_const.c: New test.

0 files changed, 0 insertions, 0 deletions