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authorMichael Collison <collison@rivosinc.com>2023-05-06 12:27:07 -0600
committerJeff Law <jlaw@ventanamicro>2023-05-06 12:27:07 -0600
commit9217e0dde1b7dbcff456d513334496404e626437 (patch)
treeeab3c1eb9fe60ccb367d1cb336208fe8633ff584 /gcc/cp/constexpr.cc
parentb9b7981f3d6919518372daf4c7e8c40dfc58f49d (diff)
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RISC-V:autovec: Add target vectorization hooks
gcc/ * config/riscv/riscv.cc (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE. (riscv_empty_mask_is_expensive): Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. (riscv_vectorize_create_costs): Implement TARGET_VECTORIZE_CREATE_COSTS. (riscv_support_vector_misalignment): Implement TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT. (TARGET_ESTIMATED_POLY_VALUE): Register target macro. (TARGET_VECTORIZE_GET_MASK_MODE): Ditto. (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto. (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
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