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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-07-27 19:47:02 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-07-27 20:11:41 +0800 |
| commit | 33b153ff521e2f33acf7d076f8625d85319b731d (patch) | |
| tree | 4b9896275523129a0af26fc0685d1681346f4768 /gcc/cp/constexpr.cc | |
| parent | d0ae71c26ab9e383768160ea266f56db2e2ae43c (diff) | |
| download | gcc-33b153ff521e2f33acf7d076f8625d85319b731d.zip gcc-33b153ff521e2f33acf7d076f8625d85319b731d.tar.gz gcc-33b153ff521e2f33acf7d076f8625d85319b731d.tar.bz2 | |
RISC-V: Enable basic VLS modes support
Support && Test VLS modes load/store/reg move as well as LRA spilling
gcc/ChangeLog:
* config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add VLS modes.
(ADJUST_ALIGNMENT): Ditto.
(ADJUST_PRECISION): Ditto.
(VLS_MODES): Ditto.
(VECTOR_MODE_WITH_PREFIX): Ditto.
* config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): New macro.
* config/riscv/riscv-protos.h (riscv_v_ext_vls_mode_p): New function.
* config/riscv/riscv-v.cc (INCLUDE_ALGORITHM): Add include.
(legitimize_move): Enable basic VLS modes support.
(get_vlmul): Ditto.
(get_ratio): Ditto.
(get_vector_mode): Ditto.
* config/riscv/riscv-vector-switch.def (VLS_ENTRY): Add vls modes.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): New function.
(VLS_ENTRY): New macro.
(riscv_v_ext_mode_p): Add vls modes.
(riscv_get_v_regno_alignment): New function.
(riscv_print_operand): Add vls modes.
(riscv_hard_regno_nregs): Ditto.
(riscv_hard_regno_mode_ok): Ditto.
(riscv_regmode_natural_size): Ditto.
(riscv_vectorize_preferred_vector_alignment): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md: Ditto.
* config/riscv/autovec-vls.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Add more checks.
* gcc.target/riscv/rvv/rvv.exp: Add VLS modes tests.
* gcc.target/riscv/rvv/autovec/vls/def.h: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-13.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-14.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-15.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-16.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-17.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mov-9.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: New test.
Diffstat (limited to 'gcc/cp/constexpr.cc')
0 files changed, 0 insertions, 0 deletions