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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-08-09 09:28:51 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-08-09 09:28:51 +0000 |
| commit | 66adb8eb440d94f72f9973f63b1aac722eb1201d (patch) | |
| tree | 443565ab356338f6e52228994fadec8e90fe9233 /gcc/coverage.h | |
| parent | 23a6cb7838f73aca404e5cc25a1cfbe1064db068 (diff) | |
| download | gcc-66adb8eb440d94f72f9973f63b1aac722eb1201d.zip gcc-66adb8eb440d94f72f9973f63b1aac722eb1201d.tar.gz gcc-66adb8eb440d94f72f9973f63b1aac722eb1201d.tar.bz2 | |
[AArch64] Fixup the vget_lane RTL patterns and intrinsics
gcc/
* config/aarch64/aarch64-simd-builtins.def (get_lane_signed): Remove.
(get_lane_unsigned): Likewise.
(dup_lane_scalar): Likewise.
(get_lane): enable for VALL.
* config/aarch64/aarch64-simd.md
(aarch64_dup_lane_scalar<mode>): Remove.
(aarch64_get_lane_signed<mode>): Likewise.
(aarch64_get_lane_unsigned<mode>): Likewise.
(aarch64_get_lane_extend<GPI:mode><VDQQH:mode>): New.
(aarch64_get_lane_zero_extendsi<mode>): Likewise.
(aarch64_get_lane<mode>): Enable for all vector modes.
(aarch64_get_lanedi): Remove misleading constraints.
* config/aarch64/arm_neon.h
(__aarch64_vget_lane_any): Define.
(__aarch64_vget<q>_lane_<fpsu><8,16,32,64>): Likewise.
(vget<q>_lane_<fpsu><8,16,32,64>): Use __aarch64_vget_lane macros.
(vdup<bhsd>_lane_<su><8,16,32,64>): Likewise.
* config/aarch64/iterators.md (VDQQH): New.
(VDQQHS): Likewise.
(vwcore): Likewise.
gcc/testsuite/
* gcc.target/aarch64/scalar_intrinsics.c: Update expected
output of vdup intrinsics.
From-SVN: r201624
Diffstat (limited to 'gcc/coverage.h')
0 files changed, 0 insertions, 0 deletions