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| author | Catherine Moore <clm@codesourcery.com> | 2014-06-24 18:07:39 -0400 |
|---|---|---|
| committer | Sandra Loosemore <sandra@gcc.gnu.org> | 2014-06-24 18:07:39 -0400 |
| commit | ecc6304308f19c159a9df27d0bd5a66f5acbba83 (patch) | |
| tree | 616d460f0f31bb751c3841d6306510ad0ecc7b41 /gcc/config | |
| parent | fc3a2e70f4e362b52cf73453667613ffce27167c (diff) | |
| download | gcc-ecc6304308f19c159a9df27d0bd5a66f5acbba83.zip gcc-ecc6304308f19c159a9df27d0bd5a66f5acbba83.tar.gz gcc-ecc6304308f19c159a9df27d0bd5a66f5acbba83.tar.bz2 | |
mips.c (mips_order_regs_for_local_alloc): Delete.
2014-06-24 Catherine Moore <clm@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
gcc/
* config/mips/mips.c (mips_order_regs_for_local_alloc): Delete.
* config/mips/mips.h (ADJUST_REG_ALLOC_ORDER): Delete.
* config/mips/mips-protos.h (mips_order_regs_for_local_alloc): Delete.
Co-Authored-By: Sandra Loosemore <sandra@codesourcery.com>
From-SVN: r211959
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips-protos.h | 1 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 22 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 7 |
3 files changed, 0 insertions, 30 deletions
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 0b32a70..8a517ee 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -247,7 +247,6 @@ extern bool mips_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT, extern bool mips_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT, HOST_WIDE_INT); extern bool mips_mem_fits_mode_p (enum machine_mode mode, rtx x); -extern void mips_order_regs_for_local_alloc (void); extern HOST_WIDE_INT mips_debugger_offset (rtx, HOST_WIDE_INT); extern void mips_push_asm_switch (struct mips_asm_switch *); diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b1504ee..10efc27 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -17497,28 +17497,6 @@ mips_conditional_register_usage (void) } } -/* When generating MIPS16 code, we want to allocate $24 (T_REG) before - other registers for instructions for which it is possible. This - encourages the compiler to use CMP in cases where an XOR would - require some register shuffling. */ - -void -mips_order_regs_for_local_alloc (void) -{ - int i; - - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - reg_alloc_order[i] = i; - - if (TARGET_MIPS16) - { - /* It really doesn't matter where we put register 0, since it is - a fixed register anyhow. */ - reg_alloc_order[0] = 24; - reg_alloc_order[24] = 0; - } -} - /* Implement EH_USES. */ bool diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7029e04..1164b4b 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2046,13 +2046,6 @@ enum reg_class 182,183,184,185,186,187 \ } -/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order - to be rearranged based on a particular function. On the mips16, we - want to allocate $24 (T_REG) before other registers for - instructions for which it is possible. */ - -#define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc () - /* True if VALUE is an unsigned 6-bit number. */ #define UIMM6_OPERAND(VALUE) \ |