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| author | Uros Bizjak <uros@gcc.gnu.org> | 2017-12-21 20:00:28 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-12-21 20:00:28 +0100 |
| commit | cb4b152d88b9c77f552345917601d401010dc4b3 (patch) | |
| tree | b50c571c96b42119ec68231cc9711e0a520dcfc9 /gcc/config | |
| parent | 056cf43428e87bff0703ab4a6ec3558a90328be4 (diff) | |
| download | gcc-cb4b152d88b9c77f552345917601d401010dc4b3.zip gcc-cb4b152d88b9c77f552345917601d401010dc4b3.tar.gz gcc-cb4b152d88b9c77f552345917601d401010dc4b3.tar.bz2 | |
re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.
testsuite/ChangeLog:
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
From-SVN: r255949
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 26 |
1 files changed, 16 insertions, 10 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index c6ab79a..59d9245 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10353,7 +10353,7 @@ (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand") + (match_operand:SI 2 "register_operand" "c,r") (match_operand:SI 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands) @@ -10367,14 +10367,15 @@ (ashift:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = gen_lowpart (QImode, operands[2]);") + "operands[2] = gen_lowpart (QImode, operands[2]);" + [(set_attr "isa" "*,bmi2")]) (define_insn_and_split "*ashl<mode>3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (and:QI - (match_operand:QI 2 "register_operand") + (match_operand:QI 2 "register_operand" "c,r") (match_operand:QI 3 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands) @@ -10387,7 +10388,9 @@ [(set (match_dup 0) (ashift:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])]) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "isa" "*,bmi2")]) (define_insn "*bmi2_ashl<mode>3_1" [(set (match_operand:SWI48 0 "register_operand" "=r") @@ -10873,7 +10876,7 @@ (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand") + (match_operand:SI 2 "register_operand" "c,r") (match_operand:SI 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) @@ -10887,14 +10890,15 @@ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = gen_lowpart (QImode, operands[2]);") + "operands[2] = gen_lowpart (QImode, operands[2]);" + [(set_attr "isa" "*,bmi2")]) (define_insn_and_split "*<shift_insn><mode>3_mask_1" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (and:QI - (match_operand:QI 2 "register_operand") + (match_operand:QI 2 "register_operand" "c,r") (match_operand:QI 3 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) @@ -10907,7 +10911,9 @@ [(set (match_dup 0) (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))])]) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "isa" "*,bmi2")]) (define_insn_and_split "*<shift_insn><mode>3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=&r") @@ -11352,7 +11358,7 @@ (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand") + (match_operand:SI 2 "register_operand" "c") (match_operand:SI 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) @@ -11373,7 +11379,7 @@ (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (and:QI - (match_operand:QI 2 "register_operand") + (match_operand:QI 2 "register_operand" "c") (match_operand:QI 3 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) |