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| author | John David Anglin <dave.anglin@nrc-cnrc.gc.ca> | 2008-09-07 19:54:30 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2008-09-07 19:54:30 +0000 |
| commit | be2f06ed3d5b59d19971e529889f185e9c2bc6c6 (patch) | |
| tree | 02d72a6839218ef5d3e6d89af6a3b5aba32e63a8 /gcc/config | |
| parent | d6ab7b032fe0def8912502dad23a4dc588269803 (diff) | |
| download | gcc-be2f06ed3d5b59d19971e529889f185e9c2bc6c6.zip gcc-be2f06ed3d5b59d19971e529889f185e9c2bc6c6.tar.gz gcc-be2f06ed3d5b59d19971e529889f185e9c2bc6c6.tar.bz2 | |
pa32-regs.h (IRA_COVER_CLASSES): Define.
* pa32-regs.h (IRA_COVER_CLASSES): Define.
* pa64-regs.h (IRA_COVER_CLASSES): Define.
From-SVN: r140093
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/pa/pa32-regs.h | 13 | ||||
| -rw-r--r-- | gcc/config/pa/pa64-regs.h | 15 |
2 files changed, 27 insertions, 1 deletions
diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index 89cbb9b..4463c63 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -287,6 +287,19 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */ +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ +} + /* Defines invalid mode changes. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 828265f..ec86560 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -235,12 +235,25 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {{0x00000000, 0x00000000}, /* NO_REGS */ \ {0x00000002, 0x00000000}, /* R1_REGS */ \ {0xfffffffe, 0x00000000}, /* GENERAL_REGS */ \ - {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \ + {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \ {0x00000000, 0x0fffffff}, /* FP_REGS */ \ {0xfffffffe, 0x0fffffff}, /* GENERAL_OR_FP_REGS */ \ {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0x1fffffff}} /* ALL_REGS */ +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ +} + /* Defines invalid mode changes. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |