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| author | Christophe Lyon <christophe.lyon@st.com> | 2019-09-10 09:56:43 +0200 |
|---|---|---|
| committer | Christophe Lyon <clyon@gcc.gnu.org> | 2019-09-10 09:56:43 +0200 |
| commit | bb33a88e3d4746470d3f969c6d764d20d726f9f1 (patch) | |
| tree | 47a9200cf7cbd1df26092ec6909cc05b0c2796a3 /gcc/config | |
| parent | ae1152e5a01301c9dfec42fc5c117a9b782e353e (diff) | |
| download | gcc-bb33a88e3d4746470d3f969c6d764d20d726f9f1.zip gcc-bb33a88e3d4746470d3f969c6d764d20d726f9f1.tar.gz gcc-bb33a88e3d4746470d3f969c6d764d20d726f9f1.tar.bz2 | |
[ARM/FDPIC v6 12/24] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp
We call __aeabi_read_tp() to get the thread pointer. Since this is a
function call, we have to restore the FDPIC register afterwards.
2019-09-10 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
gcc/
* config/arm/arm.c (arm_load_tp): Add FDPIC support.
* config/arm/arm.md (FDPIC_REGNUM): New constant.
(load_tp_soft_fdpic): New pattern.
(load_tp_soft): Disable in FDPIC mode.
Co-Authored-By: Mickaël Guêné <mickael.guene@st.com>
From-SVN: r275574
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/arm.c | 13 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 16 |
2 files changed, 27 insertions, 2 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5f1d2d4..c452771 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8685,7 +8685,18 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + emit_insn (gen_restore_pic_register_after_call(fdpic_reg, initial_fdpic_reg)); + } + else + emit_insn (gen_load_tp_soft ()); tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 027febb..918271d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -31,6 +31,7 @@ [(R0_REGNUM 0) ; First CORE register (R1_REGNUM 1) ; Second CORE register (R4_REGNUM 4) ; Fifth CORE register + (FDPIC_REGNUM 9) ; FDPIC register (IP_REGNUM 12) ; Scratch register (SP_REGNUM 13) ; Stack pointer (LR_REGNUM 14) ; Return address register @@ -11165,12 +11166,25 @@ ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI FDPIC_REGNUM)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob") + (set_attr "type" "branch")] +) + +;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")] |