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author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-12-20 22:56:49 +0800 |
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committer | Kito Cheng <kito.cheng@sifive.com> | 2022-12-23 13:41:23 +0800 |
commit | b47b33c799bd4874a4c81fb71708ff1c3dd150ff (patch) | |
tree | 107e0c78ba7b29c2355b66a795c14c72a50a875a /gcc/config | |
parent | 37fd10fd3eb42ea4487d93521a267ba08a9f8575 (diff) | |
download | gcc-b47b33c799bd4874a4c81fb71708ff1c3dd150ff.zip gcc-b47b33c799bd4874a4c81fb71708ff1c3dd150ff.tar.gz gcc-b47b33c799bd4874a4c81fb71708ff1c3dd150ff.tar.bz2 |
RISC-V: Remove side effects of vsetvl pattern in RTL.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects.
* config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern.
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 | ||||
-rw-r--r-- | gcc/config/riscv/vector.md | 26 |
2 files changed, 27 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 75879de..c1193db 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -75,7 +75,7 @@ public: /* MU. */ e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); - return e.generate_insn (code_for_vsetvl (Pmode)); + return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode)); } }; diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 52ca6b3..fd8e285 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -585,6 +585,32 @@ [(set_attr "type" "vsetvl") (set_attr "mode" "<MODE>")]) +;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects. +;; Since we have many optmization passes from "expand" to "reload_completed", +;; such pattern can allow us gain benefits of these optimizations. +(define_insn_and_split "@vsetvl<mode>_no_side_effects" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (match_operand 2 "const_int_operand" "i") + (match_operand 3 "const_int_operand" "i") + (match_operand 4 "const_int_operand" "i") + (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))] + "TARGET_VECTOR" + "#" + "&& epilogue_completed" + [(parallel + [(set (match_dup 0) + (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3) + (match_dup 4) (match_dup 5)] UNSPEC_VSETVL)) + (set (reg:SI VL_REGNUM) + (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL)) + (set (reg:SI VTYPE_REGNUM) + (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4) + (match_dup 5)] UNSPEC_VSETVL))])] + "" + [(set_attr "type" "vsetvl") + (set_attr "mode" "SI")]) + ;; RVV machine description matching format ;; (define_insn "" ;; [(set (match_operand:MODE 0) |