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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2011-03-09 00:21:53 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2011-03-09 00:21:53 +0000 |
| commit | 93b826f0fd2c0520a092322b50027974a9b9a2c5 (patch) | |
| tree | cc7fa828658e47431ee1599ef6e39eb12c1b5b52 /gcc/config | |
| parent | 84fdf81b8aa9c4fef1a43b852eb125dd124eb6e1 (diff) | |
| download | gcc-93b826f0fd2c0520a092322b50027974a9b9a2c5.zip gcc-93b826f0fd2c0520a092322b50027974a9b9a2c5.tar.gz gcc-93b826f0fd2c0520a092322b50027974a9b9a2c5.tar.bz2 | |
Fix PR 47755 fallout
From-SVN: r170802
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8609c63..b6d1a94 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4946,6 +4946,29 @@ easy_altivec_constant (rtx op, enum machine_mode mode) else if (mode != GET_MODE (op)) return false; + /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy + constants. */ + if (mode == V2DFmode) + return zero_constant (op, mode); + + if (mode == V2DImode) + { + /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not + easy. */ + if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT + || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT) + return false; + + if (zero_constant (op, mode)) + return true; + + if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1 + && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1) + return true; + + return false; + } + /* Start with a vspltisw. */ step = GET_MODE_NUNITS (mode) / 4; copies = 1; @@ -5022,8 +5045,16 @@ output_vec_const_move (rtx *operands) vec = operands[1]; mode = GET_MODE (dest); - if (TARGET_VSX && zero_constant (vec, mode)) - return "xxlxor %x0,%x0,%x0"; + if (TARGET_VSX) + { + if (zero_constant (vec, mode)) + return "xxlxor %x0,%x0,%x0"; + + if (mode == V2DImode + && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1 + && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1) + return "vspltisw %0,-1"; + } if (TARGET_ALTIVEC) { |