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author | Joseph Myers <joseph@codesourcery.com> | 2008-09-05 16:39:40 +0100 |
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committer | Joseph Myers <jsm28@gcc.gnu.org> | 2008-09-05 16:39:40 +0100 |
commit | 7314c7dd6297c6e7ebb823c1e3589c246f9349b5 (patch) | |
tree | b8f10beff854b1400e8d8d2b400046c99ccc7a67 /gcc/config | |
parent | ebac6d9cb9f255b379fffcff4ba871d5b74d39d7 (diff) | |
download | gcc-7314c7dd6297c6e7ebb823c1e3589c246f9349b5.zip gcc-7314c7dd6297c6e7ebb823c1e3589c246f9349b5.tar.gz gcc-7314c7dd6297c6e7ebb823c1e3589c246f9349b5.tar.bz2 |
mips.h (enum reg_class): Add FRAME_REGS.
* config/mips/mips.h (enum reg_class): Add FRAME_REGS.
(REG_CLASS_NAMES): Update.
(REG_CLASS_CONTENTS): Update.
* config/mips/mips.c (mips_regno_to_class): Use FRAME_REGS instead
of ALL_REGS for regs 77 and 78.
* function.c (instantiate_virtual_regs_in_insn): Assert that
return value of simplify_gen_subreg is not NULL.
testsuite:
* gcc.c-torture/compile/20080903-1.c: New test.
From-SVN: r140035
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/mips/mips.c | 2 | ||||
-rw-r--r-- | gcc/config/mips/mips.h | 5 |
2 files changed, 5 insertions, 2 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index fd0101b..33f7e87 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -502,7 +502,7 @@ const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { MD0_REG, MD1_REG, NO_REGS, ST_REGS, ST_REGS, ST_REGS, ST_REGS, ST_REGS, ST_REGS, ST_REGS, ST_REGS, NO_REGS, - NO_REGS, ALL_REGS, ALL_REGS, NO_REGS, + NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 1a9b542..4145699 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1791,6 +1791,7 @@ enum reg_class ST_REGS, /* status registers (fp status) */ DSP_ACC_REGS, /* DSP accumulator registers */ ACC_REGS, /* Hi/Lo and DSP accumulator registers */ + FRAME_REGS, /* $arg and $frame */ ALL_REGS, /* all registers */ LIM_REG_CLASSES /* max value + 1 */ }; @@ -1832,6 +1833,7 @@ enum reg_class "ST_REGS", \ "DSP_ACC_REGS", \ "ACC_REGS", \ + "FRAME_REGS", \ "ALL_REGS" \ } @@ -1874,7 +1876,8 @@ enum reg_class { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \ { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \ - { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \ + { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* frame registers */ \ + { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \ } |