mips.h (ISA_HAS_SEQ_SNE): New macro.

	* config/mips/mips.h (ISA_HAS_SEQ_SNE): New macro.
	* config/mips/mips.c (mips_expand_scc): Also expand seq and sne if
	second operand is a reg_imm10_operand.
	* config/mips/mips.md (*seq_<GPR:mode><GPR2:mode>_seq,
	*sne_<GPR:mode><GPR2:mode>_sne): New patterns.
	(*seq_<GPR:mode><GPR2:mode>): Rename to
	*seq_zero_<GPR:mode><GPR2:mode>.  Don't match if
	ISA_HAS_SEQ_SNE.
	(*seq_<GPR:mode><GPR2:mode>_mips16): Rename to
	*seq_zero_<GPR:mode><GPR2:mode>_mip16.  Don't match if
	ISA_HAS_SEQ_SNE.
	(*sne_<GPR:mode><GPR2:mode>): Rename to
	*sne_zero_<GPR:mode><GPR2:mode>.  Don't match if
	ISA_HAS_SEQ_SNE.

testsuite/
	* gcc.target/mips/seq-1.c: New test.
	* gcc.target/mips/octeon-seq-1.c: New test.
	* gcc.target/mips/octeon-seq-2.c: New test.
	* gcc.target/mips/octeon-seq-3.c: New test.
	* gcc.target/mips/octeon-seq-4.c: New test.
	* gcc.target/mips/scc-2.c: Also pass on sltiu.
	* gcc.target/mips/scc-3.c: Likewise.

From-SVN: r140010

3 files changed, 43 insertions, 8 deletions

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 911f93c..fd0101b 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4222,8 +4222,14 @@ mips_expand_scc (enum rtx_code code, rtx target)
 
   if (code == EQ || code == NE)
     {
-      rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
-      mips_emit_binary (code, target, zie, const0_rtx);
+      if (ISA_HAS_SEQ_SNE
+	  && reg_imm10_operand (cmp_operands[1], GET_MODE (cmp_operands[1])))
+	mips_emit_binary (code, target, cmp_operands[0], cmp_operands[1]);
+      else
+	{
+	  rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
+	  mips_emit_binary (code, target, zie, const0_rtx);
+	}
     }
   else
     mips_emit_int_order_test (code, 0, target,
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 4677546..1a9b542 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1015,6 +1015,9 @@ enum mips_code_readable_setting {
 /* ISA includes the exts instruction.  */
 #define ISA_HAS_EXTS		TARGET_OCTEON
 
+/* ISA includes the seq and sne instructions.  */
+#define ISA_HAS_SEQ_SNE		TARGET_OCTEON
+
 /* ISA includes the pop instruction.  */
 #define ISA_HAS_POP		TARGET_OCTEON
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 0f478cf..0512a70 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5200,24 +5200,37 @@
   ""
   { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
 
-(define_insn "*seq_<GPR:mode><GPR2:mode>"
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
   [(set (match_operand:GPR2 0 "register_operand" "=d")
 	(eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
 		 (const_int 0)))]
-  "!TARGET_MIPS16"
+  "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
   "sltu\t%0,%1,1"
   [(set_attr "type" "slt")
    (set_attr "mode" "<GPR:MODE>")])
 
-(define_insn "*seq_<GPR:mode><GPR2:mode>_mips16"
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
   [(set (match_operand:GPR2 0 "register_operand" "=t")
 	(eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
 		 (const_int 0)))]
-  "TARGET_MIPS16"
+  "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
   "sltu\t%1,1"
   [(set_attr "type" "slt")
    (set_attr "mode" "<GPR:MODE>")])
 
+;; Generate sltiu unless using seq results in better code.
+(define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
+  [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+	(eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+		 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+  "ISA_HAS_SEQ_SNE"
+  "@
+   seq\t%0,%1,%2
+   sltiu\t%0,%1,1
+   seqi\t%0,%1,%2"
+  [(set_attr "type" "slt")
+   (set_attr "mode" "<GPR:MODE>")])
+
 ;; "sne" uses sltu instructions in which the first operand is $0.
 ;; This isn't possible in mips16 code.
 
@@ -5228,15 +5241,28 @@
   "!TARGET_MIPS16"
   { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
 
-(define_insn "*sne_<GPR:mode><GPR2:mode>"
+(define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
   [(set (match_operand:GPR2 0 "register_operand" "=d")
 	(ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
 		 (const_int 0)))]
-  "!TARGET_MIPS16"
+  "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
   "sltu\t%0,%.,%1"
   [(set_attr "type" "slt")
    (set_attr "mode" "<GPR:MODE>")])
 
+;; Generate sltu unless using sne results in better code.
+(define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
+  [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+	(ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+		 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+  "ISA_HAS_SEQ_SNE"
+  "@
+   sne\t%0,%1,%2
+   sltu\t%0,%.,%1
+   snei\t%0,%1,%2"
+  [(set_attr "type" "slt")
+   (set_attr "mode" "<GPR:MODE>")])
+
 (define_expand "sgt<u>"
   [(set (match_operand:SI 0 "register_operand")
 	(any_gt:SI (match_dup 1)