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| author | Jim Wilson <jim.wilson@linaro.org> | 2015-06-19 17:22:38 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2015-06-19 10:22:38 -0700 |
| commit | 490948ca36a1b9dc407930eba0e6dd52c83dac4d (patch) | |
| tree | dd73baf67c8ce5485b478e5f8cbef72b8bac78cd /gcc/config | |
| parent | 590f5d5125c96aa8e6e29463e37f23502f0bd673 (diff) | |
| download | gcc-490948ca36a1b9dc407930eba0e6dd52c83dac4d.zip gcc-490948ca36a1b9dc407930eba0e6dd52c83dac4d.tar.gz gcc-490948ca36a1b9dc407930eba0e6dd52c83dac4d.tar.bz2 | |
aarch64.md (mov<mode>:GPF): Don't call force_reg if op1 is an fp zero.
gcc/
* config/aarch64/aarch64.md (mov<mode>:GPF): Don't call force_reg if
op1 is an fp zero.
(movsf_aarch64): Change condition from register_operand to
aarch64_reg_or_fp_zero for op1. Change type for alternative 6 to
load1. Change type for alternative 7 to store1.
(movdf_aarch64): Likewise.
gcc/testsuite/
* gcc.target/aarch64/fmovd-zero-mem.c: New.
* gcc.target/aarch64/fmovd-zero-reg.c: New.
* gcc.target/aarch64/fmovf-zero-mem.c: New.
* gcc.target/aarch64/fmovf-zero-reg.c: New.
* gcc.target/aarch64/fmovld-zero-mem.c: New.
* gcc.target/aarch64/fmovld-zero-mem.c: New.
* gcc.target/aarch64/fmovd-zero.c: Delete.
* gcc.target/aarch64/fmovf-zero.c: Delete.
From-SVN: r224673
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1efe57c..d3f5d5b 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -986,7 +986,9 @@ FAIL; } - if (GET_CODE (operands[0]) == MEM) + if (GET_CODE (operands[0]) == MEM + && ! (GET_CODE (operands[1]) == CONST_DOUBLE + && aarch64_float_const_zero_rtx_p (operands[1]))) operands[1] = force_reg (<MODE>mode, operands[1]); " ) @@ -995,7 +997,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:SF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" + || aarch64_reg_or_fp_zero (operands[1], SFmode))" "@ fmov\\t%s0, %w1 fmov\\t%w0, %s1 @@ -1007,14 +1009,14 @@ str\\t%w1, %0 mov\\t%w0, %w1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,f_loads,f_stores,mov_reg")] + f_loads,f_stores,load1,store1,mov_reg")] ) (define_insn "*movdf_aarch64" [(set (match_operand:DF 0 "nonimmediate_operand" "=w, ?r,w,w ,w,m,r,m ,r") (match_operand:DF 1 "general_operand" "?rY, w,w,Ufc,m,w,m,rY,r"))] "TARGET_FLOAT && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + || aarch64_reg_or_fp_zero (operands[1], DFmode))" "@ fmov\\t%d0, %x1 fmov\\t%x0, %d1 @@ -1026,7 +1028,7 @@ str\\t%x1, %0 mov\\t%x0, %x1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,f_loadd,f_stored,mov_reg")] + f_loadd,f_stored,load1,store1,mov_reg")] ) (define_expand "movtf" |