diff options
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2018-01-03 02:38:09 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2018-01-03 02:38:09 +0000 |
| commit | 2d71e7b8d45597f9905580cf645dbe047385cb13 (patch) | |
| tree | 402ee0fb80510f03a8e436d10d0a6b48b95272cd /gcc/config | |
| parent | 50d75500a3342f0bb73da86675b7e41e5a928ea4 (diff) | |
| download | gcc-2d71e7b8d45597f9905580cf645dbe047385cb13.zip gcc-2d71e7b8d45597f9905580cf645dbe047385cb13.tar.gz gcc-2d71e7b8d45597f9905580cf645dbe047385cb13.tar.bz2 | |
rs6000.md (floor<mode>2): Add support for IEEE 128-bit round to integer instructions.
[gcc]
2018-01-02 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (floor<mode>2): Add support for IEEE
128-bit round to integer instructions.
(ceil<mode>2): Likewise.
(btrunc<mode>2): Likewise.
(round<mode>2): Likewise.
[gcc/testsuite]
2018-01-02 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/float128-hw2.c: Add tests for ceilf128,
floorf128, truncf128, and roundf128.
* gcc.target/powerpc/float128-hw5.c: New tests for _Float128
optimizations added in match.pd.
* gcc.target/powerpc/float128-hw6.c: Likewise.
* gcc.target/powerpc/float128-hw7.c: Likewise.
* gcc.target/powerpc/float128-hw8.c: Likewise.
* gcc.target/powerpc/float128-hw9.c: Likewise.
* gcc.target/powerpc/float128-hw10.c: Likewise.
* gcc.target/powerpc/float128-hw11.c: Likewise.
From-SVN: r256118
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2c310d7..531b1ee 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14777,6 +14777,47 @@ (set_attr "type" "vecfloat") (set_attr "size" "128")]) +;; IEEE 128-bit round to integer built-in functions +(define_insn "floor<mode>2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + (unspec:IEEE128 + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + UNSPEC_FRIM))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "xsrqpi 1,%0,%1,3" + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) + +(define_insn "ceil<mode>2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + (unspec:IEEE128 + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + UNSPEC_FRIP))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "xsrqpi 1,%0,%1,2" + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) + +(define_insn "btrunc<mode>2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + (unspec:IEEE128 + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + UNSPEC_FRIZ))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "xsrqpi 1,%0,%1,1" + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) + +(define_insn "round<mode>2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + (unspec:IEEE128 + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] + UNSPEC_FRIN))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" + "xsrqpi 0,%0,%1,0" + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) + ;; IEEE 128-bit instructions with round to odd semantics (define_insn "add<mode>3_odd" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") |