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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-12-23 11:33:06 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-12-23 13:42:04 +0800 |
| commit | 16eb1f43ab4e521ed4503e7766eee25da75eaeba (patch) | |
| tree | 578ffb9a59bb8601cd2df6a0dd457daa707ec502 /gcc/config | |
| parent | a143c3f7a61c61bb5a5e099fdb59f3adbf99b6b3 (diff) | |
| download | gcc-16eb1f43ab4e521ed4503e7766eee25da75eaeba.zip gcc-16eb1f43ab4e521ed4503e7766eee25da75eaeba.tar.gz gcc-16eb1f43ab4e521ed4503e7766eee25da75eaeba.tar.bz2 | |
RISC-V: Fix vle constraints
gcc/ChangeLog:
* config/riscv/vector.md: Fix contraints.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-constraint-1.c: New test.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/vector.md | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index fd8e285..6455aee 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -656,18 +656,18 @@ ;; 2. (const_vector:VNx1SF repeat [ ;; (const_double:SF 0.0 [0x0.0p+0])]). (define_insn_and_split "@pred_mov<mode>" - [(set (match_operand:V 0 "nonimmediate_operand" "=vd, vr, m, vr, vr") + [(set (match_operand:V 0 "nonimmediate_operand" "=vd, vr, m, vr, vr") (if_then_else:V (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" " vm, Wc1, vmWc1, Wc1, Wc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1, vmWc1, Wc1, Wc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand:V 3 "vector_move_operand" " m, m, vr, vr, viWc0") - (match_operand:V 2 "vector_merge_operand" " 0, vu, vu0, vu0, vu0")))] + (match_operand:V 3 "vector_move_operand" " m, m, vr, vr, viWc0") + (match_operand:V 2 "vector_merge_operand" " 0, vu, vu0, vu0, vu0")))] "TARGET_VECTOR" "@ vle<sew>.v\t%0,%3%p1 |