S/390: Introduce relative_long attribute

In order to properly fix PR87762, we need to distinguish between
instructions which support relative addressing and instructions which
don't.  We could check whether the existing "type" attribute is equal to
"larl", but there are notable exceptions (lrl, for example), and
changing them makes scheduling worse on z10.  We could also check
whether the existing "op_type" attribute is equal to "RIL-b" or "RIL-c".
However, adding a new attribute provides more flexibility, since we
don't depend idiosyncrasies which might be introduced into PoP in the
future.

gcc/ChangeLog:

2018-11-06  Ilya Leoshkevich  <iii@linux.ibm.com>

	PR target/87762
	* config/s390/s390.md: Add relative_long attribute.

From-SVN: r265844

1 files changed, 67 insertions, 27 deletions

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 4ffd438..957c378 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -570,6 +570,13 @@
 	 ]
 	(const_int 0)))
 
+;; Whether an instruction supports relative long addressing.
+;; Currently this corresponds to RIL-b and RIL-c instruction formats,
+;; but having a separate attribute, as opposed to reusing op_type,
+;; provides additional flexibility.
+
+(define_attr "relative_long" "no,yes" (const_string "no"))
+
 ;; Pipeline description for z900.
 (include "2064.md")
 
@@ -1130,7 +1137,8 @@
    cgfrl\t%0,%1"
   [(set_attr "op_type"      "RRE,RXY,RIL")
    (set_attr "z10prop" "z10_c,*,*")
-   (set_attr "type"         "*,*,larl")])
+   (set_attr "type"         "*,*,larl")
+   (set_attr "relative_long" "*,*,yes")])
 
 
 
@@ -1146,7 +1154,8 @@
   [(set_attr "op_type"      "RX,RXY,RIL")
    (set_attr "cpu_facility" "*,longdisp,z10")
    (set_attr "type"         "*,*,larl")
-   (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
+   (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")
+   (set_attr "relative_long" "*,*,yes")])
 
 (define_insn "*cmphi_ccs_z10"
   [(set (reg CC_REGNUM)
@@ -1166,7 +1175,8 @@
    cgh\t%0,%1
    cghrl\t%0,%1"
   [(set_attr "op_type" "RXY,RIL")
-   (set_attr "type"    "*,larl")])
+   (set_attr "type"    "*,larl")
+   (set_attr "relative_long" "*,yes")])
 
 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
 (define_insn "*cmp<mode>_ccs"
@@ -1187,7 +1197,8 @@
   [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
    (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
    (set_attr "type" "*,*,*,*,*,*,larl")
-   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")
+   (set_attr "relative_long" "*,*,*,*,*,*,yes")])
 
 
 ; Compare (unsigned) instructions
@@ -1201,7 +1212,8 @@
   "clhrl\t%0,%1"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "larl")
-   (set_attr "z10prop" "z10_super")])
+   (set_attr "z10prop" "z10_super")
+   (set_attr "relative_long" "yes")])
 
 ; clhrl, clghrl
 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
@@ -1213,7 +1225,8 @@
   "cl<g>hrl\t%0,%1"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "larl")
-   (set_attr "z10prop" "z10_super")])
+   (set_attr "z10prop" "z10_super")
+   (set_attr "relative_long" "yes")])
 
 (define_insn "*cmpdi_ccu_zero"
   [(set (reg CC_REGNUM)
@@ -1228,7 +1241,8 @@
   [(set_attr "op_type"      "RRE,RXY,RIL")
    (set_attr "cpu_facility" "*,*,z10")
    (set_attr "type"         "*,*,larl")
-   (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
+   (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")
+   (set_attr "relative_long" "*,*,yes")])
 
 (define_insn "*cmpdi_ccu"
   [(set (reg CC_REGNUM)
@@ -1248,7 +1262,8 @@
   [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
    (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
    (set_attr "type"         "*,*,larl,*,*,*,*")
-   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")
+   (set_attr "relative_long" "*,*,yes,*,*,*,*")])
 
 (define_insn "*cmpsi_ccu"
   [(set (reg CC_REGNUM)
@@ -1267,7 +1282,8 @@
   [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
    (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
    (set_attr "type"         "*,*,larl,*,*,*,*,*")
-   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
+   (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")
+   (set_attr "relative_long" "*,*,yes,*,*,*,*,*")])
 
 (define_insn "*cmphi_ccu"
   [(set (reg CC_REGNUM)
@@ -1805,6 +1821,10 @@
                         *,
                         *,*,*,*,*,*,*,
                         z10_super_A1")
+   (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,
+                              *,yes,*,*,*,*,*,*,*,*,
+                              yes,*,*,*,*,*,*,*,*,*,
+                              *,*,yes")
 ])
 
 (define_split
@@ -1997,7 +2017,8 @@
   "larl\t%0,%1"
    [(set_attr "op_type" "RIL")
     (set_attr "type"    "larl")
-    (set_attr "z10prop" "z10_fwd_A1")])
+    (set_attr "z10prop" "z10_fwd_A1")
+    (set_attr "relative_long" "yes")])
 
 (define_insn "*movsi_zarch"
   [(set (match_operand:SI 0 "nonimmediate_operand"
@@ -2087,7 +2108,10 @@
                         *,
                         z10_rec,
                         z10_super,
-                        *,*,*,*,*,*,*")])
+                        *,*,*,*,*,*,*")
+   (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*,
+                              *,*,*,*,*,*,*,*,*,*,
+                              *,yes,*,*,*,*,*,*,*,*")])
 
 (define_insn "*movsi_esa"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
@@ -2254,7 +2278,8 @@
                        z10_rec,
                        z10_rec,
                        z10_rec,
-                       z10_super,*,*,*,*,*,*")])
+                       z10_super,*,*,*,*,*,*")
+   (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")])
 
 (define_peephole2
   [(set (match_operand:HI 0 "register_operand" "")
@@ -2543,7 +2568,8 @@
    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
                      fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store")
    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*")
-   (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")])
+   (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")
+   (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")])
 
 (define_insn "*mov<mode>_64"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T")
@@ -2566,7 +2592,8 @@
    (set_attr "type"    "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
                         fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
    (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
-   (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")])
+   (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")
+   (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")])
 
 (define_insn "*mov<mode>_31"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
@@ -2674,7 +2701,8 @@
    (set_attr "type"    "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
                         fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
    (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
-   (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
+   (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")
+   (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")])
 
 ;
 ; movcc instruction pattern
@@ -2968,7 +2996,8 @@
    && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
   "exrl\t%1,%3"
   [(set_attr "op_type" "RIL")
-   (set_attr "type"    "cs")])
+   (set_attr "type"    "cs")
+   (set_attr "relative_long" "yes")])
 
 (define_insn "*execute"
   [(match_parallel 0 "execute_operation"
@@ -4471,7 +4500,8 @@
   [(set_attr "op_type"      "RRE,RXY,RIL")
    (set_attr "type"         "*,*,larl")
    (set_attr "cpu_facility" "*,*,z10")
-   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")
+   (set_attr "relative_long" "*,*,yes")])
 
 ;
 ; extend(hi|qi)(si|di)2 instruction pattern(s).
@@ -4515,7 +4545,8 @@
   [(set_attr "op_type"      "RRE,RXY,RIL")
    (set_attr "type"         "*,*,larl")
    (set_attr "cpu_facility" "extimm,extimm,z10")
-   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")
+   (set_attr "relative_long" "*,*,yes")])
 
 (define_insn "*extendhidi2"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -4541,7 +4572,8 @@
   [(set_attr "op_type"      "RRE,RX,RXY,RIL")
    (set_attr "type"         "*,*,*,larl")
    (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
-   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+   (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")
+   (set_attr "relative_long" "*,*,*,yes")])
 
 (define_insn "*extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -4626,7 +4658,8 @@
   [(set_attr "op_type"      "RRE,RXY,RIL")
    (set_attr "type"         "*,*,larl")
    (set_attr "cpu_facility" "*,*,z10")
-   (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
+   (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")
+   (set_attr "relative_long" "*,*,yes")])
 
 ;
 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
@@ -4739,7 +4772,8 @@
   [(set_attr "op_type"      "RXY,RRE,RIL")
    (set_attr "type"         "*,*,larl")
    (set_attr "cpu_facility" "*,*,z10")
-   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
+   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")
+   (set_attr "relative_long" "*,*,yes")])
 
 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
@@ -9952,7 +9986,8 @@
   "brasl\t%2,%0"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "jsr")
-   (set_attr "z196prop" "z196_cracked")])
+   (set_attr "z196prop" "z196_cracked")
+   (set_attr "relative_long" "yes")])
 
 (define_insn "*basr"
   [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
@@ -10058,7 +10093,8 @@
   "brasl\t%3,%1"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "jsr")
-   (set_attr "z196prop" "z196_cracked")])
+   (set_attr "z196prop" "z196_cracked")
+   (set_attr "relative_long" "yes")])
 
 (define_insn "*basr_r"
   [(set (match_operand 0 "" "")
@@ -10201,7 +10237,8 @@
   "brasl\t%3,%1%J4"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "jsr")
-   (set_attr "z196prop" "z196_cracked")])
+   (set_attr "z196prop" "z196_cracked")
+   (set_attr "relative_long" "yes")])
 
 (define_insn "*basr_tls"
   [(set (match_operand 0 "" "")
@@ -10736,7 +10773,8 @@
   [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
   ""
   "brcl\t0, 0"
-  [(set_attr "op_type" "RIL")])
+  [(set_attr "op_type" "RIL")
+   (set_attr "relative_long" "yes")])
 
 
 ;
@@ -10789,7 +10827,8 @@
   "larl\t%0,%1"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "larl")
-   (set_attr "z10prop" "z10_fwd_A1")])
+   (set_attr "z10prop" "z10_fwd_A1")
+   (set_attr "relative_long" "yes")])
 
 (define_insn "main_pool"
   [(set (match_operand 0 "register_operand" "=a")
@@ -11075,7 +11114,8 @@
   [(set_attr "type" "load,larl")
    (set_attr "op_type" "RXY,RIL")
    (set_attr "z10prop" "z10_super")
-   (set_attr "z196prop" "z196_alone")])
+   (set_attr "z196prop" "z196_alone")
+   (set_attr "relative_long" "yes")])
 
 
 ;