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| author | Jeff Law <jlaw@ventanamicro.com> | 2022-12-27 16:57:09 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2022-12-27 16:57:09 -0700 |
| commit | 103f963e5cf6e7fe80395efc5fcede351420e25d (patch) | |
| tree | bdec3e3012154ef4136bdd1bbaab64ec956c07e3 /gcc/config | |
| parent | 2e886eef7f2b5aadb00171af868f0895b647c3a4 (diff) | |
| download | gcc-103f963e5cf6e7fe80395efc5fcede351420e25d.zip gcc-103f963e5cf6e7fe80395efc5fcede351420e25d.tar.gz gcc-103f963e5cf6e7fe80395efc5fcede351420e25d.tar.bz2 | |
Commit right version of last patch (missing modes)
gcc/
* config/riscv/riscv.md: Add missing modes to last patch.t
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv.md | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 020833b..a10cee2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1677,7 +1677,8 @@ (define_insn_and_split "*mvconst_internal" [(set (match_operand:GPR 0 "register_operand" "=r") (match_operand:GPR 1 "splittable_const_int_operand" "i"))] - "!(p2m1_shift_operand (operands[1]) || high_mask_shift_operand (operands[1]))" + "!(p2m1_shift_operand (operands[1], <MODE>mode) + || high_mask_shift_operand (operands[1], <MODE>mode))" "#" "&& 1" [(const_int 0)] |