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| author | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2017-03-24 13:52:30 +0000 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2017-03-24 13:52:30 +0000 |
| commit | 085db63d5899052fa0cf8c09e51b9ebaf5c5fb0c (patch) | |
| tree | b131b32e8a988e3abb690c01244ae7791152812e /gcc/config | |
| parent | dc4f29bc9a9dfcc68b20c0ce767cc3d6fb7409d4 (diff) | |
| download | gcc-085db63d5899052fa0cf8c09e51b9ebaf5c5fb0c.zip gcc-085db63d5899052fa0cf8c09e51b9ebaf5c5fb0c.tar.gz gcc-085db63d5899052fa0cf8c09e51b9ebaf5c5fb0c.tar.bz2 | |
S/390: PR79904: Disallow reg + sym_ref literal pool addresses.
We accept reg + sym_ref as valid address if sym_ref is a literal pool
reference knowing that it will be rewritten as r13 + reg + offset.
However, annotate_constant_pool_refs was never able to handle that.
With the patch only single sym_refs are accepted.
Regression tested on s390x.
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
PR target/79904
* config/s390/s390.c (s390_decompose_address): Reject reg +
sym_ref literal pool references.
gcc/testsuite/ChangeLog:
2017-03-24 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* gcc.dg/ubsan/pr79904-2.c: New test.
From-SVN: r246443
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/s390/s390.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index e7ab128..27640ad 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -2842,13 +2842,10 @@ s390_decompose_address (rtx addr, struct s390_address *out) displacements by basing them off the base register. */ if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp)) { - /* Either base or index must be free to hold the base register. */ - if (!base) - base = fake_pool_base, literal_pool = true; - else if (!indx) - indx = fake_pool_base, literal_pool = true; - else - return false; + if (base || indx) + return false; + + base = fake_pool_base, literal_pool = true; /* Mark up the displacement. */ disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), |