bfin-modes.def, [...]: Follow spelling conventions.

	* config/bfin/bfin-modes.def, config/bfin/bfin.c,
	config/bfin/bfin.md, config/bfin/predicates.md: Follow
	spelling conventions.

From-SVN: r121577

4 files changed, 14 insertions, 14 deletions

diff --git a/gcc/config/bfin/bfin-modes.def b/gcc/config/bfin/bfin-modes.def
index b48665f..f39f9bd 100644
--- a/gcc/config/bfin/bfin-modes.def
+++ b/gcc/config/bfin/bfin-modes.def
@@ -19,7 +19,7 @@
    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-/* PDImode for the 40 bit accumulators.  */
+/* PDImode for the 40-bit accumulators.  */
 PARTIAL_INT_MODE (DI);
 
 /* Two of those - covering both accumulators for vector multiplications.  */
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index e31ced1..0d46f61 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -576,7 +576,7 @@ add_to_reg (rtx reg, HOST_WIDE_INT value, int frame)
     return;
 
   /* Choose whether to use a sequence using a temporary register, or
-     a sequence with multiple adds.  We can add a signed 7 bit value
+     a sequence with multiple adds.  We can add a signed 7-bit value
      in one instruction.  */
   if (value > 120 || value < -120)
     {
@@ -1080,7 +1080,7 @@ bfin_delegitimize_address (rtx orig_x)
 
 /* This predicate is used to compute the length of a load/store insn.
    OP is a MEM rtx, we return nonzero if its addressing mode requires a
-   32 bit instruction.  */
+   32-bit instruction.  */
 
 int
 effective_address_32bit_p (rtx op, enum machine_mode mode) 
@@ -1102,7 +1102,7 @@ effective_address_32bit_p (rtx op, enum machine_mode mode)
 
   offset = INTVAL (XEXP (op, 1));
 
-  /* All byte loads use a 16 bit offset.  */
+  /* All byte loads use a 16-bit offset.  */
   if (GET_MODE_SIZE (mode) == 1)
     return 1;
 
@@ -1889,7 +1889,7 @@ hard_regno_mode_ok (int regno, enum machine_mode mode)
   if (mode == PDImode || mode == V2PDImode)
     return regno == REG_A0 || regno == REG_A1;
 
-  /* Allow all normal 32 bit regs, except REG_M3, in case regclass ever comes
+  /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
      up with a bad register class (such as ALL_REGS) for DImode.  */
   if (mode == DImode)
     return regno < REG_M3;
@@ -2243,7 +2243,7 @@ bfin_gen_compare (rtx cmp, enum machine_mode mode ATTRIBUTE_UNUSED)
 }
 
 /* Return nonzero iff C has exactly one bit set if it is interpreted
-   as a 32 bit constant.  */
+   as a 32-bit constant.  */
 
 int
 log2constp (unsigned HOST_WIDE_INT c)
@@ -3977,7 +3977,7 @@ bfin_reorg (void)
       schedule_insns ();
       timevar_pop (TV_SCHED2);
 
-      /* Examine the schedule and insert nops as necessary for 64 bit parallel
+      /* Examine the schedule and insert nops as necessary for 64-bit parallel
 	 instructions.  */
       bfin_gen_bundles ();
     }
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 8a59ce8..8c088f9 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -136,7 +136,7 @@
    (UNSPEC_MOVE_FDPIC 8)
    (UNSPEC_FUNCDESC_GOT17M4 9)
    (UNSPEC_LSETUP_END 10)
-   ;; Distinguish a 32 bit version of an insn from a 16 bit version.
+   ;; Distinguish a 32-bit version of an insn from a 16-bit version.
    (UNSPEC_32BIT 11)])
 
 (define_constants
@@ -190,7 +190,7 @@
 (define_cpu_unit "slot2" "bfin")
 
 ;; Three units used to enforce parallel issue restrictions:
-;; only one of the 16 bit slots can use a P register in an address,
+;; only one of the 16-bit slots can use a P register in an address,
 ;; and only one them can be a store.
 (define_cpu_unit "store" "bfin")
 (define_cpu_unit "pregs" "bfin")
@@ -2675,7 +2675,7 @@
   ""
   "")
 
-;; Unusual arithmetic operations on 16 bit registers.
+;; Unusual arithmetic operations on 16-bit registers.
 
 (define_insn "ssaddhi3"
   [(set (match_operand:HI 0 "register_operand" "=d")
@@ -2883,7 +2883,7 @@
 ;; an unspec with a const_int operand that determines which flag to use in the
 ;; instruction.
 ;; There are variants for single and parallel multiplications.
-;; There are variants which just use 16 bit lowparts as inputs, and variants
+;; There are variants which just use 16-bit lowparts as inputs, and variants
 ;; which allow the user to choose just which halves to use as input values.
 ;; There are variants which set D registers, variants which set accumulators,
 ;; variants which set both, some of them optionally using the accumulators as
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index a0a7960..528792c 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -96,7 +96,7 @@
   (and (match_code "reg")
        (match_test "REGNO (op) == REG_LB0 || REGNO (op) == REG_LB1")))
 
-;; Return nonzero if OP is a register or a 7 bit signed constant.
+;; Return nonzero if OP is a register or a 7-bit signed constant.
 (define_predicate "reg_or_7bit_operand"
   (ior (match_operand 0 "register_operand")
        (and (match_code "const_int")
@@ -119,7 +119,7 @@
   (ior (match_operand 0 "nondp_register_operand")
        (match_operand 0 "memory_operand")))
 
-;; Return nonzero if OP is a register or, when negated, a 7 bit signed
+;; Return nonzero if OP is a register or, when negated, a 7-bit signed
 ;; constant.
 (define_predicate "reg_or_neg7bit_operand"
   (ior (match_operand 0 "register_operand")
@@ -180,7 +180,7 @@
 ;; The following two are used to compute the addrtype attribute.  They return
 ;; true if passed a memory address usable for a 16-bit load or store using a
 ;; P or I register, respectively.  If neither matches, we know we have a
-;; 32 bit instruction.
+;; 32-bit instruction.
 (define_predicate "mem_p_address_operand"
   (match_code "mem")
 {