sh.c (reg_class_from_letter): Assign `k' to SIBCALL_REGS.

* config/sh/sh.c (reg_class_from_letter): Assign `k' to SIBCALL_REGS.
(machine_dependent_reorg): Split all insns.
* config/sh/sh.h (CONDITIONAL_REGISTER_USAGE): Compute
reg_class_contents[SIBCALL_REGS].
(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add SIBCALL_REGS.
* config/sh/sh.md (calli_pcrel, call_pcrel, call_valuei_pcrel,
call_value_pcrel, call, call_value, sibcall): Match even when
not optimizing.
(sibcalli_pcrel, sibcall_pcrel): Likewise.  Use constraint `k'
for call address.
(sibcalli): Likewise.

From-SVN: r37934

3 files changed, 28 insertions, 17 deletions

diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 80b1808..8f25be8 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -120,7 +120,7 @@ enum reg_class reg_class_from_letter[] =
 {
   /* a */ ALL_REGS, /* b */ NO_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
   /* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
-  /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
+  /* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
   /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
   /* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
   /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
@@ -2913,6 +2913,12 @@ machine_dependent_reorg (first)
   rtx r0_rtx = gen_rtx_REG (Pmode, 0);
   rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
 
+  /* We must split call insns before introducing `mova's.  If we're
+     optimizing, they'll have already been split.  Otherwise, make
+     sure we don't split them too late.  */
+  if (! optimize)
+    split_all_insns (0);
+
   /* If relaxing, generate pseudo-ops to associate function calls with
      the symbols they call.  It does no harm to not generate these
      pseudo-ops.  However, when we can generate them, it enables to
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index b411a52..076539e 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -63,17 +63,17 @@ extern int code_for_indirect_jump_scratch;
 /* We can not debug without a frame pointer.  */
 /* #define CAN_DEBUG_WITHOUT_FP */
 
-#define CONDITIONAL_REGISTER_USAGE					\
+#define CONDITIONAL_REGISTER_USAGE do					\
+{									\
+  int regno;								\
   if (! TARGET_SH4 || ! TARGET_FMOVD)					\
     {									\
-      int regno;							\
       for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++)		\
 	fixed_regs[regno] = call_used_regs[regno] = 1;			\
       if (! TARGET_SH4)							\
 	{								\
 	  if (! TARGET_SH3E)						\
 	    {								\
-	      int regno;						\
 	      for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++)	\
 		fixed_regs[regno] = call_used_regs[regno] = 1;		\
 	      fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1;	\
@@ -87,7 +87,11 @@ extern int code_for_indirect_jump_scratch;
     {									\
       call_used_regs[MACH_REG] = 0;					\
       call_used_regs[MACL_REG] = 0;					\
-    }
+    }									\
+  for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)	\
+    if (! fixed_regs[regno] && call_used_regs[regno])			\
+      SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);	\
+} while (0)
 
 /* ??? Need to write documentation for all SH options and add it to the
    invoke.texi file.  */
@@ -712,6 +716,7 @@ enum reg_class
   T_REGS,
   MAC_REGS,
   FPUL_REGS,
+  SIBCALL_REGS,
   GENERAL_REGS,
   FP0_REGS,
   FP_REGS,
@@ -733,6 +738,7 @@ enum reg_class
   "T_REGS",		\
   "MAC_REGS",		\
   "FPUL_REGS",		\
+  "SIBCALL_REGS",	\
   "GENERAL_REGS",	\
   "FP0_REGS",		\
   "FP_REGS",		\
@@ -754,6 +760,8 @@ enum reg_class
   { 0x00040000, 0x00000000 }, /* T_REGS		*/	\
   { 0x00300000, 0x00000000 }, /* MAC_REGS	*/	\
   { 0x00400000, 0x00000000 }, /* FPUL_REGS	*/	\
+  /* SIBCALL_REGS is initialized in CONDITIONAL_REGISTER_USAGE.  */ \
+  { 0x00000000, 0x00000000 }, /* SIBCALL_REGS   */	\
   { 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS	*/	\
   { 0x01000000, 0x00000000 }, /* FP0_REGS	*/	\
   { 0xFF000000, 0x000000FF }, /* FP_REGS	*/	\
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 901fd52..8904831 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -3410,7 +3410,7 @@
    (use (reg:SI PIC_REG))
    (clobber (reg:SI PR_REG))
    (clobber (match_scratch:SI 2 "=r"))]
-  "TARGET_SH2 && optimize"
+  "TARGET_SH2"
   "#"
   "reload_completed"
   [(const_int 0)]
@@ -3469,7 +3469,7 @@
    (use (reg:SI PIC_REG))
    (clobber (reg:SI PR_REG))
    (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_SH2 && optimize"
+  "TARGET_SH2"
   "#"
   "reload_completed"
   [(const_int 0)]
@@ -3499,7 +3499,7 @@
   ""
   "
 {
-  if (flag_pic && TARGET_SH2 && optimize
+  if (flag_pic && TARGET_SH2
       && GET_CODE (operands[0]) == MEM
       && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
     {
@@ -3519,7 +3519,7 @@
   ""
   "
 {
-  if (flag_pic && TARGET_SH2 && optimize
+  if (flag_pic && TARGET_SH2
       && GET_CODE (operands[1]) == MEM
       && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
     {
@@ -3532,8 +3532,7 @@
 }")
 
 (define_insn "sibcalli"
-  ;; FIXME: any call-clobbered register will do
-  [(call (mem:SI (match_operand:SI 0 "register_operand" "z"))
+  [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
 	 (match_operand 1 "" ""))
    (use (reg:PSI FPSCR_REG))
    (return)]
@@ -3543,8 +3542,7 @@
    (set_attr "type" "jump_ind")])
 
 (define_insn "sibcalli_pcrel"
-  ;; FIXME: any call-clobbered register will do
-  [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "z"))
+  [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
 	 (match_operand 1 "" ""))
    (use (match_operand 2 "" ""))
    (use (reg:PSI FPSCR_REG))
@@ -3558,10 +3556,9 @@
   [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
 	 (match_operand 1 "" ""))
    (use (reg:PSI FPSCR_REG))
-   ;; FIXME: any call-clobbered register will do
-   (clobber (match_scratch:SI 2 "=z"))
+   (clobber (match_scratch:SI 2 "=k"))
    (return)]
-  "TARGET_SH2 && optimize"
+  "TARGET_SH2"
   "#"
   "reload_completed"
   [(const_int 0)]
@@ -3586,7 +3583,7 @@
   ""
   "
 {
-  if (flag_pic && TARGET_SH2 && optimize
+  if (flag_pic && TARGET_SH2
       && GET_CODE (operands[0]) == MEM
       && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
       /* The PLT needs the PIC register, but the epilogue would have