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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-11-16 10:55:40 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-11-16 10:55:40 +0000 |
| commit | 6544cb5289824d813ab580746ab2748da6fa59e5 (patch) | |
| tree | a3da43c50663f12e4e056b62f0067f8551991092 /gcc/config | |
| parent | f75cdd2c4e5282985a6fbdb2e72e17cb77782044 (diff) | |
| download | gcc-6544cb5289824d813ab580746ab2748da6fa59e5.zip gcc-6544cb5289824d813ab580746ab2748da6fa59e5.tar.gz gcc-6544cb5289824d813ab580746ab2748da6fa59e5.tar.bz2 | |
[AArch64] Replace SVE_PARTIAL with SVE_PARTIAL_I
Another renaming, this time to make way for partial/unpacked
float modes.
2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (SVE_PARTIAL): Rename to...
(SVE_PARTIAL_I): ...this.
* config/aarch64/aarch64-sve.md: Apply the above renaming throughout.
From-SVN: r278339
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 16 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 88eaaa3..5b71ab0 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2818,33 +2818,33 @@ ;; ------------------------------------------------------------------------- ;; Predicated SXT[BHW]. -(define_insn "@aarch64_pred_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL:mode>" +(define_insn "@aarch64_pred_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>" [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w") (unspec:SVE_FULL_HSDI [(match_operand:<VPRED> 1 "register_operand" "Upl") (sign_extend:SVE_FULL_HSDI - (truncate:SVE_PARTIAL + (truncate:SVE_PARTIAL_I (match_operand:SVE_FULL_HSDI 2 "register_operand" "w")))] UNSPEC_PRED_X))] "TARGET_SVE && (~<narrower_mask> & <self_mask>) == 0" - "sxt<SVE_PARTIAL:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype>" + "sxt<SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype>" ) ;; Predicated SXT[BHW] with merging. -(define_insn "@aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL:mode>" +(define_insn "@aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>" [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w, ?&w, ?&w") (unspec:SVE_FULL_HSDI [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl") (sign_extend:SVE_FULL_HSDI - (truncate:SVE_PARTIAL + (truncate:SVE_PARTIAL_I (match_operand:SVE_FULL_HSDI 2 "register_operand" "w, w, w"))) (match_operand:SVE_FULL_HSDI 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && (~<narrower_mask> & <self_mask>) == 0" "@ - sxt<SVE_PARTIAL:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype> - movprfx\t%0.<SVE_FULL_HSDI:Vetype>, %1/z, %2.<SVE_FULL_HSDI:Vetype>\;sxt<SVE_PARTIAL:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype> - movprfx\t%0, %3\;sxt<SVE_PARTIAL:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype>" + sxt<SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype> + movprfx\t%0.<SVE_FULL_HSDI:Vetype>, %1/z, %2.<SVE_FULL_HSDI:Vetype>\;sxt<SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype> + movprfx\t%0, %3\;sxt<SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_HSDI:Vetype>, %1/m, %2.<SVE_FULL_HSDI:Vetype>" [(set_attr "movprfx" "*,yes,yes")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 890b3a8..fc27179 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -339,10 +339,10 @@ ;; Fully-packed SVE vector modes that have 64-bit elements. (define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF]) -;; All partial SVE modes. -(define_mode_iterator SVE_PARTIAL [VNx2QI - VNx4QI VNx2HI - VNx8QI VNx4HI VNx2SI]) +;; All partial SVE integer modes. +(define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI + VNx4HI VNx2HI + VNx2SI]) ;; Modes involved in extending or truncating SVE data, for 8 elements per ;; 128-bit block. |