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| author | Dragan Mladjenovic <draganm@gcc.gnu.org> | 2019-11-19 18:14:32 +0000 |
|---|---|---|
| committer | Dragan Mladjenovic <draganm@gcc.gnu.org> | 2019-11-19 18:14:32 +0000 |
| commit | 4aa5fd8aca1140adf0917dc53397efddc7fd4c11 (patch) | |
| tree | 1702499848761bf8961de779a0e6c7d4c2ca3596 /gcc/config | |
| parent | aa5355781fd8746cb2ac8f0e456f8ac6dc4bf9c5 (diff) | |
| download | gcc-4aa5fd8aca1140adf0917dc53397efddc7fd4c11.zip gcc-4aa5fd8aca1140adf0917dc53397efddc7fd4c11.tar.gz gcc-4aa5fd8aca1140adf0917dc53397efddc7fd4c11.tar.bz2 | |
[MIPS] Prevent MSA branches from being put into delay slots
This patch tightens the instruction definitions to make sure
that MSA branch instructions cannot be put into delay slots and have their
delay slots eligible for being filled. Also, MSA *div*3 patterns use MSA
branches for zero checks but are not marked as being multi instruction and
thus could be put into delay slots. This patch fixes that.
gcc/ChangeLog:
2019-11-19 Zoran Jovanovic <zoran.jovanovic@mips.com>
Dragan Mladjenovic <dmladjenovic@wavecomp.com>
* config/mips/mips-msa.md (msa_<msabr>_<msafmt_f>, msa_<msabr>_v_<msafmt_f>):
Mark as not having "likely" version.
* config/mips/mips.md (insn_count): The simd_div instruction with
TARGET_CHECK_ZERO_DIV consists of 3 instructions.
(can_delay): Exclude simd_branch.
(defile_delay *): Add simd_branch instructions.
They have one regular delay slot.
gcc/testsuite/ChangeLog:
2019-11-19 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
* gcc.target/mips/msa-ds.c: New test.
From-SVN: r278458
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips-msa.md | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 10 |
2 files changed, 12 insertions, 4 deletions
diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 628423d..100cf99 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -2719,7 +2719,8 @@ } [(set_attr "type" "simd_branch") (set_attr "mode" "<MODE>") - (set_attr "compact_form" "never")]) + (set_attr "compact_form" "never") + (set_attr "branch_likely" "no")]) (define_insn "msa_<msabr>_v_<msafmt_f>" [(set (pc) (if_then_else @@ -2738,4 +2739,5 @@ } [(set_attr "type" "simd_branch") (set_attr "mode" "TI") - (set_attr "compact_form" "never")]) + (set_attr "compact_form" "never") + (set_attr "branch_likely" "no")]) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4de9731..929e368 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -560,6 +560,12 @@ (eq_attr "type" "idiv,idiv3") (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))") + ;; simd div have 3 instruction if TARGET_CHECK_ZERO_DIV is true. + (eq_attr "type" "simd_div") + (if_then_else (match_test "TARGET_CHECK_ZERO_DIV") + (const_int 3) + (const_int 1)) + (not (eq_attr "sync_mem" "none")) (symbol_ref "mips_sync_loop_insns (insn, operands)")] (const_int 1))) @@ -759,7 +765,7 @@ ;; Can the instruction be put into a delay slot? (define_attr "can_delay" "no,yes" - (if_then_else (and (eq_attr "type" "!branch,call,jump") + (if_then_else (and (eq_attr "type" "!branch,call,jump,simd_branch") (eq_attr "hazard" "none") (match_test "get_attr_insn_count (insn) == 1")) (const_string "yes") @@ -1098,7 +1104,7 @@ ;; Branches that have delay slots and don't have likely variants do ;; not annul on false. -(define_delay (and (eq_attr "type" "branch") +(define_delay (and (eq_attr "type" "branch,simd_branch") (not (match_test "TARGET_MIPS16")) (ior (match_test "TARGET_CB_NEVER") (and (eq_attr "compact_form" "maybe") |