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| author | Uros Bizjak <uros@kss-loka.si> | 2004-02-12 00:39:41 +0100 |
|---|---|---|
| committer | Roger Sayle <sayle@gcc.gnu.org> | 2004-02-11 23:39:41 +0000 |
| commit | 3b8e0c9129b0ed3fe2e4aa5bc466df5348e2d5fd (patch) | |
| tree | 159c66f75d67ab22ee9d79a474ed9f6f66eab4ba /gcc/config | |
| parent | a6abdce327180878f4753126647b351026b2dcd0 (diff) | |
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optabs.h (enum optab_index): Add new OTI_log10 and OTI_log2.
2004-02-11 Uros Bizjak <uros@kss-loka.si>
* optabs.h (enum optab_index): Add new OTI_log10 and OTI_log2.
(log10_optab, log2_optab): Define corresponding macros.
* optabs.c (init_optabs): Initialize log10_optab and log2_optab.
* genopinit.c (optabs): Implement log10_optab and log2_optab
using log10?f2 and log2?f2 patterns.
* builtins.c (expand_builtin_mathfn): Handle BUILT_IN_LOG10{,F,L}
using log10_optab, and BUILT_IN_LOG2{,F,L} using log2_optab.
(expand_builtin): Expand BUILT_IN_LOG10{,F,L} and BUILT_IN_LOG2{,F,L}
using expand_builtin_mathfn if flag_unsafe_math_optimizations is set.
* config/i386/i386.md (log10sf2, log10df2, log10xf2, log2sf2,
log2df2, log2xf2): New patterns to implement log10, log10f, log10l,
log2, log2f and log2l built-ins as inline x87 intrinsics.
* gcc.dg/builtins-33.c: New test.
From-SVN: r77675
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2c7bbb4..70c21f8 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15154,6 +15154,88 @@ emit_move_insn (operands[2], temp); }) +(define_expand "log10sf2" + [(parallel [(set (match_operand:SF 0 "register_operand" "") + (unspec:SF [(match_operand:SF 1 "register_operand" "") + (match_dup 2)] UNSPEC_FYL2X)) + (clobber (match_scratch:SF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + rtx temp; + + operands[2] = gen_reg_rtx (XFmode); + temp = standard_80387_constant_rtx (3); /* fldlg2 */ + emit_move_insn (operands[2], temp); +}) + +(define_expand "log10df2" + [(parallel [(set (match_operand:DF 0 "register_operand" "") + (unspec:DF [(match_operand:DF 1 "register_operand" "") + (match_dup 2)] UNSPEC_FYL2X)) + (clobber (match_scratch:DF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + rtx temp; + + operands[2] = gen_reg_rtx (XFmode); + temp = standard_80387_constant_rtx (3); /* fldlg2 */ + emit_move_insn (operands[2], temp); +}) + +(define_expand "log10xf2" + [(parallel [(set (match_operand:XF 0 "register_operand" "") + (unspec:XF [(match_operand:XF 1 "register_operand" "") + (match_dup 2)] UNSPEC_FYL2X)) + (clobber (match_scratch:XF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + rtx temp; + + operands[2] = gen_reg_rtx (XFmode); + temp = standard_80387_constant_rtx (3); /* fldlg2 */ + emit_move_insn (operands[2], temp); +}) + +(define_expand "log2sf2" + [(parallel [(set (match_operand:SF 0 "register_operand" "") + (unspec:SF [(match_operand:SF 1 "register_operand" "") + (match_dup 2)] UNSPEC_FYL2X)) + (clobber (match_scratch:SF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + operands[2] = gen_reg_rtx (XFmode); + emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ + +}) + +(define_expand "log2df2" + [(parallel [(set (match_operand:DF 0 "register_operand" "") + (unspec:DF [(match_operand:DF 1 "register_operand" "") + (match_dup 2)] UNSPEC_FYL2X)) + (clobber (match_scratch:DF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + operands[2] = gen_reg_rtx (XFmode); + emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ +}) + +(define_expand "log2xf2" + [(parallel [(set (match_operand:XF 0 "register_operand" "") + (unspec:XF [(match_operand:XF 1 "register_operand" "") + (match_dup 2)] UNSPEC_FYL2X)) + (clobber (match_scratch:XF 3 ""))])] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && flag_unsafe_math_optimizations" +{ + operands[2] = gen_reg_rtx (XFmode); + emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ +}) + (define_insn "*fscale_sfxf3" [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:XF 2 "register_operand" "0") |