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| author | Li Jia He <helijia@linux.ibm.com> | 2019-06-26 08:23:06 +0000 |
|---|---|---|
| committer | Li Jia He <helijia@gcc.gnu.org> | 2019-06-26 08:23:06 +0000 |
| commit | fdfbed383e48f9a6fce6ef1e0e0defea0363ac3f (patch) | |
| tree | 5ade5236ca921e53c9aa2e0b78b6a0f188de6f96 /gcc/config | |
| parent | de80936dbf2ae4a6304a8cbe70e05b483bcc7ee9 (diff) | |
| download | gcc-fdfbed383e48f9a6fce6ef1e0e0defea0363ac3f.zip gcc-fdfbed383e48f9a6fce6ef1e0e0defea0363ac3f.tar.gz gcc-fdfbed383e48f9a6fce6ef1e0e0defea0363ac3f.tar.bz2 | |
[RS6000] Change maddld match_operand from DI to GPR
From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows:
64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits,
and add them together.
We only apply it to 64-bit mode (DI) when implementing maddld. However, if we
can guarantee that the result of the maddld operation will be limited to 32-bit
mode (SI), we can still apply it to 32-bit mode (SI).
gcc/ChangeLog
2019-06-26 Li Jia He <helijia@linux.ibm.com>
* config/rs6000/rs6000.h (TARGET_MADDLD): Remove the restriction of
TARGET_POWERPC64.
* config/rs6000/rs6000.md (maddld): Change maddld match_operand from DI
to GPR.
gcc/testsuite/ChangeLog
2019-06-26 Li Jia He <helijia@linux.ibm.com>
* gcc.target/powerpc/maddld-1.c: New testcase.
From-SVN: r272673
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index a211171..0a2c0bc 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -453,7 +453,7 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIWUZ TARGET_POPCNTD #define TARGET_CTZ TARGET_MODULO #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) -#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) +#define TARGET_MADDLD TARGET_MODULO #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b04c7055..9445d5f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3062,11 +3062,11 @@ DONE; }) -(define_insn "*maddld4" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (plus:DI (mult:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "gpc_reg_operand" "r")) - (match_operand:DI 3 "gpc_reg_operand" "r")))] +(define_insn "*maddld<mode>4" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")) + (match_operand:GPR 3 "gpc_reg_operand" "r")))] "TARGET_MADDLD" "maddld %0,%1,%2,%3" [(set_attr "type" "mul")]) |