RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.

gcc/ChangeLog:

	* config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro.
	(DEF_RVV_FUNCTION): Ditto.
	(handle_pragma_vector): Add intrinsic framework.
	* config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax.
	* config/riscv/riscv.md: include vector.md.
	* config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o
	* config/riscv/riscv-vector-builtins-bases.cc: New file.
	* config/riscv/riscv-vector-builtins-bases.h: New file.
	* config/riscv/riscv-vector-builtins-functions.def: New file.
	* config/riscv/riscv-vector-builtins-shapes.cc: New file.
	* config/riscv/riscv-vector-builtins-shapes.h: New file.
	* config/riscv/riscv-vector-builtins-types.def: New file.
	* config/riscv/vector.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vsetvl-1.c: New test.

11 files changed, 549 insertions, 1 deletions

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
new file mode 100644
index 0000000..8582c0c
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -0,0 +1,104 @@
+/* function_base implementation for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "riscv-vector-builtins-bases.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements vsetvl<mode> && vsetvlmax<mode>.  */
+template<bool VLMAX_P>
+class vsetvl : public function_base
+{
+public:
+  unsigned int call_properties (const function_instance &) const
+  {
+    return CP_READ_CSR | CP_WRITE_CSR;
+  }
+
+  rtx expand (function_expander &e) const override
+  {
+    if (VLMAX_P)
+      e.add_input_operand (Pmode, gen_rtx_REG (Pmode, 0));
+    else
+      e.add_input_operand (0);
+
+    tree type = builtin_types[e.type.index].vector;
+    machine_mode mode = TYPE_MODE (type);
+    machine_mode inner_mode = GET_MODE_INNER (mode);
+    /* SEW.  */
+    e.add_input_operand (Pmode,
+			 gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode));
+
+    /* LMUL. Define the bitmap rule as follows:
+       |      4       | 3 2 1 0 |
+       | fractional_p | factor  |
+    */
+    bool fractional_p = known_lt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR);
+    unsigned int factor
+      = fractional_p ? exact_div (BYTES_PER_RISCV_VECTOR, GET_MODE_SIZE (mode))
+			 .to_constant ()
+		     : exact_div (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR)
+			 .to_constant ();
+    e.add_input_operand (Pmode,
+			 gen_int_mode ((fractional_p << 4) | factor, Pmode));
+
+    /* TA.  */
+    e.add_input_operand (Pmode, gen_int_mode (1, Pmode));
+
+    /* MU.  */
+    e.add_input_operand (Pmode, gen_int_mode (0, Pmode));
+    return e.generate_insn (code_for_vsetvl (Pmode));
+  }
+};
+
+static CONSTEXPR const vsetvl<false> vsetvl_obj;
+static CONSTEXPR const vsetvl<true> vsetvlmax_obj;
+namespace bases {
+const function_base *const vsetvl = &vsetvl_obj;
+const function_base *const vsetvlmax = &vsetvlmax_obj;
+}
+
+} // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
new file mode 100644
index 0000000..a0ae18e
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -0,0 +1,33 @@
+/* function_base declaration for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef GCC_RISCV_VECTOR_BUILTINS_BASES_H
+#define GCC_RISCV_VECTOR_BUILTINS_BASES_H
+
+namespace riscv_vector {
+
+namespace bases {
+extern const function_base *const vsetvl;
+extern const function_base *const vsetvlmax;
+}
+
+} // end namespace riscv_vector
+
+#endif
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
new file mode 100644
index 0000000..dc41537
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -0,0 +1,43 @@
+/* Intrinsic define macros for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+/* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions.
+
+     - NAME not only describes the base_name of the functions
+       but also point to the name of the function_base class.
+
+     - SHAPE point to the function_shape class.
+
+     - PREDS describes the predication types that are supported in the
+       functions.
+
+     - OPS_INFO describes all information of return type and each
+       argument type.
+
+*/
+#ifndef DEF_RVV_FUNCTION
+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
+#endif
+
+/* 6. Configuration-Setting Instructions.  */
+DEF_RVV_FUNCTION (vsetvl, vsetvl, none_preds, i_none_size_size_ops)
+DEF_RVV_FUNCTION (vsetvlmax, vsetvlmax, none_preds, i_none_size_void_ops)
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
new file mode 100644
index 0000000..24fc1c0
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -0,0 +1,104 @@
+/* function_shape implementation for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+
+namespace riscv_vector {
+
+/* Add one function instance for GROUP, using operand suffix at index OI,
+   mode suffix at index PAIR && bi and predication suffix at index pred_idx.  */
+static void
+build_one (function_builder &b, const function_group_info &group,
+	   unsigned int pred_idx, unsigned int vec_type_idx)
+{
+  /* Byte forms of non-tuple vlxusegei take 21 arguments.  */
+  auto_vec<tree, 21> argument_types;
+  function_instance function_instance (group.base_name, *group.base,
+				       *group.shape,
+				       group.ops_infos.types[vec_type_idx],
+				       group.preds[pred_idx], &group.ops_infos);
+  tree return_type = group.ops_infos.ret.get_tree_type (
+    group.ops_infos.types[vec_type_idx].index);
+  b.allocate_argument_types (function_instance, argument_types);
+  b.add_unique_function (function_instance, (*group.shape), return_type,
+			 argument_types);
+}
+
+/* Add a function instance for every operand && predicate && args
+   combination in GROUP.  Take the function base name from GROUP && operand
+   suffix from operand_suffixes && mode suffix from type_suffixes && predication
+   suffix from predication_suffixes. Use apply_predication to add in
+   the predicate.  */
+static void
+build_all (function_builder &b, const function_group_info &group)
+{
+  for (unsigned int pred_idx = 0; group.preds[pred_idx] != NUM_PRED_TYPES;
+       ++pred_idx)
+    for (unsigned int vec_type_idx = 0;
+	 group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES;
+	 ++vec_type_idx)
+      build_one (b, group, pred_idx, vec_type_idx);
+}
+
+/* Declare the function shape NAME, pointing it to an instance
+   of class <NAME>_def.  */
+#define SHAPE(DEF, VAR) \
+  static CONSTEXPR const DEF##_def VAR##_obj; \
+  namespace shapes { const function_shape *const VAR = &VAR##_obj; }
+
+/* Base class for for build.  */
+struct build_base : public function_shape
+{
+  void build (function_builder &b,
+	      const function_group_info &group) const override
+  {
+    build_all (b, group);
+  }
+};
+
+/* vsetvl_def class.  */
+struct vsetvl_def : public build_base
+{
+  char *get_name (function_builder &b, const function_instance &instance,
+		  bool overloaded_p) const override
+  {
+    /* vsetvl* instruction doesn't have C++ overloaded functions.  */
+    if (overloaded_p)
+      return nullptr;
+    b.append_name (instance.base_name);
+    b.append_name (type_suffixes[instance.type.index].vsetvl);
+    return b.finish_name ();
+  }
+};
+SHAPE(vsetvl, vsetvl)
+SHAPE(vsetvl, vsetvlmax)
+
+} // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h
new file mode 100644
index 0000000..f2d876f
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h
@@ -0,0 +1,33 @@
+/* function_shape declaration for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef GCC_RISCV_VECTOR_BUILTINS_SHAPES_H
+#define GCC_RISCV_VECTOR_BUILTINS_SHAPES_H
+
+namespace riscv_vector {
+
+namespace shapes {
+extern const function_shape *const vsetvl;
+extern const function_shape *const vsetvlmax;
+}
+
+} // end namespace riscv_vector
+
+#endif
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
new file mode 100644
index 0000000..f282a5e
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -0,0 +1,50 @@
+/* Intrinsic type iterators for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2022 Free Software Foundation, Inc.
+   Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+/* Use "DEF_ALL_SIGNED_INTEGER" macro include all signed integer which will be
+   iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_I_OPS
+#define DEF_RVV_I_OPS(TYPE, REQUIRE)
+#endif
+
+DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint8mf4_t, 0)
+DEF_RVV_I_OPS (vint8mf2_t, 0)
+DEF_RVV_I_OPS (vint8m1_t, 0)
+DEF_RVV_I_OPS (vint8m2_t, 0)
+DEF_RVV_I_OPS (vint8m4_t, 0)
+DEF_RVV_I_OPS (vint8m8_t, 0)
+DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint16mf2_t, 0)
+DEF_RVV_I_OPS (vint16m1_t, 0)
+DEF_RVV_I_OPS (vint16m2_t, 0)
+DEF_RVV_I_OPS (vint16m4_t, 0)
+DEF_RVV_I_OPS (vint16m8_t, 0)
+DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint32m1_t, 0)
+DEF_RVV_I_OPS (vint32m2_t, 0)
+DEF_RVV_I_OPS (vint32m4_t, 0)
+DEF_RVV_I_OPS (vint32m8_t, 0)
+DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+
+#undef DEF_RVV_I_OPS
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 5c20788..dc41078 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -45,6 +45,8 @@
 #include "targhooks.h"
 #include "regs.h"
 #include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "riscv-vector-builtins-bases.h"
 
 using namespace riscv_vector;
 
@@ -115,6 +117,49 @@ const char *const predication_suffixes[NUM_PRED_TYPES] = {
 #include "riscv-vector-builtins.def"
 };
 
+/* A list of all signed integer will be registered for intrinsic functions.  */
+static const rvv_type_info i_ops[] = {
+#define DEF_RVV_I_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
+static CONSTEXPR const rvv_arg_type_info rvv_arg_type_info_end
+  = rvv_arg_type_info (NUM_BASE_TYPES);
+
+/* A list of args for size_t func (void) function.  */
+static CONSTEXPR const rvv_arg_type_info void_args[]
+  = {rvv_arg_type_info (RVV_BASE_void), rvv_arg_type_info_end};
+
+/* A list of args for size_t func (size_t) function.  */
+static CONSTEXPR const rvv_arg_type_info size_args[]
+  = {rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info_end};
+
+/* A list of none preds that will be registered for intrinsic functions.  */
+static CONSTEXPR const predication_type_index none_preds[]
+  = {PRED_TYPE_none, NUM_PRED_TYPES};
+
+/* A static operand information for size_t func (void) function registration. */
+static CONSTEXPR const rvv_op_info i_none_size_void_ops
+  = {i_ops,				/* Types */
+     OP_TYPE_none,			/* Suffix */
+     rvv_arg_type_info (RVV_BASE_size), /* Return type */
+     void_args /* Args */};
+
+/* A static operand information for size_t func (size_t) function registration.
+ */
+static CONSTEXPR const rvv_op_info i_none_size_size_ops
+  = {i_ops,				/* Types */
+     OP_TYPE_none,			/* Suffix */
+     rvv_arg_type_info (RVV_BASE_size), /* Return type */
+     size_args /* Args */};
+
+/* A list of all RVV intrinsic functions.  */
+static function_group_info function_groups[] = {
+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)                         \
+  {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO},
+#include "riscv-vector-builtins-functions.def"
+};
+
 /* The RVV types, with their built-in
    "__rvv..._t" name.  Allow an index of NUM_VECTOR_TYPES, which always
    yields a null tree.  */
@@ -787,11 +832,22 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type,
 void
 handle_pragma_vector ()
 {
+  if (function_table)
+    {
+      error ("duplicate definition of %qs", "riscv_vector.h");
+      return;
+    }
   rvv_switcher rvv;
 
   /* Define the vector and tuple types.  */
   for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i)
     register_vector_type ((enum vector_type_index) type_i);
+
+  /* Define the functions.  */
+  function_table = new hash_table<registered_function_hasher> (1023);
+  function_builder builder;
+  for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
+    builder.register_function_group (function_groups[i]);
 }
 
 /* Return the function decl with RVV function subcode CODE, or error_mark_node
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ad57b99..90a3904 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4135,6 +4135,32 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 
   switch (letter)
     {
+      case 'm': {
+	if (code == CONST_INT)
+	  {
+	    /* LMUL. Define the bitmap rule as follows:
+	       |      4       | 3 2 1 0 |
+	       | fractional_p | factor  |
+	    */
+	    bool fractional_p = (UINTVAL (op) >> 4) & 0x1;
+	    unsigned int factor = UINTVAL (op) & 0xf;
+	    asm_fprintf (file, "%s%d", fractional_p ? "mf" : "m", factor);
+	  }
+	else
+	  output_operand_lossage ("invalid vector constant");
+	break;
+      }
+      case 'p': {
+	if (code == CONST_INT)
+	  {
+	    /* Tail && Mask policy.  */
+	    bool agnostic_p = UINTVAL (op) & 0x1;
+	    asm_fprintf (file, "%s", agnostic_p ? "a" : "u");
+	  }
+	else
+	  output_operand_lossage ("invalid vector constant");
+	break;
+      }
     case 'h':
       if (code == HIGH)
 	op = XEXP (op, 0);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2d1cda2..b365491 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2999,3 +2999,4 @@
 (include "pic.md")
 (include "generic.md")
 (include "sifive-7.md")
+(include "vector.md")
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 15b9e7c..8f67676 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -11,10 +11,36 @@ riscv-vector-builtins.o: $(srcdir)/config/riscv/riscv-vector-builtins.cc \
   $(FUNCTION_H) fold-const.h gimplify.h explow.h stor-layout.h $(REGS_H) \
   alias.h langhooks.h attribs.h stringpool.h \
   $(srcdir)/config/riscv/riscv-vector-builtins.h \
-  $(srcdir)/config/riscv/riscv-vector-builtins.def
+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
+  $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \
+  $(srcdir)/config/riscv/riscv-vector-builtins.def \
+  $(srcdir)/config/riscv/riscv-vector-builtins-types.def \
+  $(srcdir)/config/riscv/riscv-vector-builtins-functions.def
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/riscv/riscv-vector-builtins.cc
 
+riscv-vector-builtins-shapes.o: \
+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc \
+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \
+  $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) \
+  $(srcdir)/config/riscv/riscv-vector-builtins.h \
+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h
+	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+		$(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc
+
+riscv-vector-builtins-bases.o: \
+  $(srcdir)/config/riscv/riscv-vector-builtins-bases.cc \
+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \
+  $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \
+  $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \
+  gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \
+  rtx-vector-builder.h \
+  $(srcdir)/config/riscv/riscv-vector-builtins.h \
+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
+  $(srcdir)/config/riscv/riscv-vector-builtins-bases.h
+	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+		$(srcdir)/config/riscv/riscv-vector-builtins-bases.cc
+
 riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \
   $(SYSTEM_H) $(TM_H)
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
new file mode 100644
index 0000000..82ce902
--- /dev/null
+++ b/gcc/config/riscv/vector.md
@@ -0,0 +1,72 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2022 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; This file describes the RISC-V 'V' Extension, Version 1.0.
+;;
+;; This file include :
+;;
+;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
+;; - Auto-vectorization (TBD)
+;; - Combine optimization (TBD)
+
+(define_c_enum "unspec" [
+  UNSPEC_VSETVL
+])
+
+;; -----------------------------------------------------------------
+;; ---- 6. Configuration-Setting Instructions
+;; -----------------------------------------------------------------
+;; Includes:
+;; - 6.1 vsetvli/vsetivl/vsetvl instructions
+;; -----------------------------------------------------------------
+
+;; we dont't define vsetvli as unspec_volatile which has side effects.
+;; This instruction can be scheduled by the instruction scheduler.
+;; This means these instructions will be deleted when
+;; there is no instructions using vl or vtype in the following.
+;; rd  | rs1 | AVL value | Effect on vl
+;; -   | !x0 | x[rs1]    | Normal stripmining
+;; !x0 | x0  | ~0        | Set vl to VLMAX
+;; operands[0]: VL.
+;; operands[1]: AVL.
+;; operands[2]: SEW
+;; operands[3]: LMUL
+;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
+;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
+(define_insn "@vsetvl<mode>"
+  [(set (match_operand:P 0 "register_operand" "=r,r")
+	(unspec:P [(match_operand:P 1 "csr_operand" "r,K")
+		   (match_operand 2 "const_int_operand" "i,i")
+		   (match_operand 3 "const_int_operand" "i,i")
+		   (match_operand 4 "const_int_operand" "i,i")
+		   (match_operand 5 "const_int_operand" "i,i")] UNSPEC_VSETVL))
+   (set (reg:SI VL_REGNUM)
+	(unspec:SI [(match_dup 1)
+		    (match_dup 2)
+		    (match_dup 3)] UNSPEC_VSETVL))
+   (set (reg:SI VTYPE_REGNUM)
+	(unspec:SI [(match_dup 2)
+		    (match_dup 3)
+		    (match_dup 4)
+		    (match_dup 5)] UNSPEC_VSETVL))]
+  "TARGET_VECTOR"
+  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
+  [(set_attr "type" "vsetvl")
+   (set_attr "mode" "<MODE>")])