ChangeLog.2, [...]: Fix spelling errors.

	* ChangeLog.2, ChangeLog.4, ChangeLog.5, ChangeLog,
	FSFChangeLog.10, FSFChangeLog.11, alias.c, attribs.c,
	caller-save.c, calls.c, cfg.c, cfganal.c, cfgcleanup.c, cfgrtl.c,
	cppmacro.c, fold-const.c, ifcvt.c, local-alloc.c, profile.c,
	sched-int.h, toplev.c, config/alpha/alpha.c,
	config/alpha/alpha.md, config/c4x/c4x.h, config/cris/cris.h,
	config/cris/cris.md, config/i370/i370.md, config/i386/i386.c,
	config/i386/i386.h, config/i386/i386.md, config/i386/xm-djgpp.h,
	config/ia64/ia64.c, config/m68hc11/m68hc11.c, config/m68k/m68k.md,
	config/mcore/mcore.h, config/mmix/mmix.c, config/ns32k/ns32k.h,
	config/ns32k/ns32k.md, config/rs6000/rs6000.c,
	config/rs6000/sysv4.h, config/sh/sh.md: Fix spelling errors.

From-SVN: r46760

20 files changed, 47 insertions, 47 deletions

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 4affac3..511db59 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -7618,7 +7618,7 @@ alpha_align_insns (insns, max_align, next_group, next_nop)
     }
 }
 
-/* Machine dependant reorg pass.  */
+/* Machine dependent reorg pass.  */
 
 void
 alpha_reorg (insns)
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 25eb09e..8594c82 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -84,7 +84,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   [(set_attr "type" "multi")])
 
 ;; Define the operand size an insn operates on.  Used primarily by mul
-;; and div operations that have size dependant timings.
+;; and div operations that have size dependent timings.
 
 (define_attr "opsize" "si,di,udi"
   (const_string "di"))
@@ -284,13 +284,13 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   (and (eq_attr "cpu" "ev5")
        (and (eq_attr "type" "fdiv")
 	    (eq_attr "opsize" "si")))
-  15 15)				; 15 to 31 data dependant
+  15 15)				; 15 to 31 data dependent
 
 (define_function_unit "fdiv" 1 0
   (and (eq_attr "cpu" "ev5")
        (and (eq_attr "type" "fdiv")
 	    (eq_attr "opsize" "di")))
-  22 22)				; 22 to 60 data dependant
+  22 22)				; 22 to 60 data dependent
 
 ;; EV6 scheduling.  EV6 can issue 4 insns per clock.
 ;;
@@ -433,7 +433,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
 ;; sign-extend.
 
 ;; Handle 32-64 bit extension from memory to a floating point register
-;; specially, since this ocurrs frequently in int->double conversions.
+;; specially, since this occurs frequently in int->double conversions.
 ;;
 ;; Note that while we must retain the =f case in the insn for reload's
 ;; benefit, it should be eliminated after reload, so we should never emit
@@ -6643,7 +6643,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   "trapb"
   [(set_attr "type" "misc")])
 
-;; No-op instructions used by machine-dependant reorg to preserve
+;; No-op instructions used by machine-dependent reorg to preserve
 ;; alignment for instruction issue.
 ;; The Unicos/Mk assembler does not support these opcodes.
 
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
index 8b5025c..924642a 100644
--- a/gcc/config/c4x/c4x.h
+++ b/gcc/config/c4x/c4x.h
@@ -1555,7 +1555,7 @@ CUMULATIVE_ARGS;
    The problem is a subtle one and deals with the manner in which the
    negative condition (N) flag is used on the C4x.  This flag does not
    reflect the status of the actual result but of the ideal result had
-   no overflow occured (when considering signed operands).
+   no overflow occurred (when considering signed operands).
 
    For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0.  Here
    the flags reflect the untruncated result, not the actual result.
@@ -1591,7 +1591,7 @@ CUMULATIVE_ARGS;
    To handle the problem where the N flag is set differently whenever
    there is an overflow we use a different CC mode, CC_NOOVmode which
    says that the CC reflects the comparison of the result against zero
-   if no overflow occured.
+   if no overflow occurred.
 
    For example, 
 
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index 31d8971..2857788 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -122,7 +122,7 @@ extern const char *cris_elinux_stacksize_str;
    Note that for -melinux and -mlinux, command-line -isystem options are
    emitted both before and after the synthesized one.  We can't remove all
    of them: a %{<isystem} will only remove the first one and %{<isystem*}
-   will not do TRT.  Those extra occurences are harmless anyway.  */
+   will not do TRT.  Those extra occurrences are harmless anyway.  */
 #define CPP_SPEC \
  "-$ -D__CRIS_ABI_version=2\
   %{mtune=*:-D__tune_%* %{mtune=v*:-D__CRIS_arch_tune=%*}}\
@@ -199,7 +199,7 @@ extern const char *cris_elinux_stacksize_str;
    are linked in (multilibbing).  The somewhat cryptic -rpath-link pair is
    to avoid *only* picking up the linux multilib subdir from the "-B./"
    option during build, while still giving it preference.  We'd need some
-   %s-variant that checked for existance of some specific file.  */
+   %s-variant that checked for existence of some specific file.  */
 /* Override previous definitions (svr4.h).  */
 #undef LINK_SPEC
 #define LINK_SPEC \
@@ -294,7 +294,7 @@ extern int target_flags;
 #define TARGET_MASK_DATA_ALIGN 128
 #define TARGET_DATA_ALIGN (target_flags & TARGET_MASK_DATA_ALIGN)
 
-/* If not to omit funtion prologue and epilogue.  */
+/* If not to omit function prologue and epilogue.  */
 #define TARGET_MASK_PROLOGUE_EPILOGUE 256
 #define TARGET_PROLOGUE_EPILOGUE (target_flags & TARGET_MASK_PROLOGUE_EPILOGUE)
 
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 3df8aaa..dedf8a8 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -2635,7 +2635,7 @@
 ;; second operand, and the third operand is -256 or -65536, we can use
 ;; CLEAR instead.  Or, if the first operand is a register, and the third
 ;; operand is 255 or 65535, we can zero_extend.
-;; GCC isnt smart enough to recognize these cases (yet), and they seem
+;; GCC isn't smart enough to recognize these cases (yet), and they seem
 ;; to be common enough to be worthwhile.
 ;; FIXME: This should be made obsolete.
 
diff --git a/gcc/config/i370/i370.md b/gcc/config/i370/i370.md
index c0d05e6..b6da211 100644
--- a/gcc/config/i370/i370.md
+++ b/gcc/config/i370/i370.md
@@ -1964,7 +1964,7 @@ check_label_emit ();
   "*
 {
   check_label_emit ();
-  CC_STATUS_INIT;  /* add assumes CC but LA doesnt set CC */
+  CC_STATUS_INIT;  /* add assumes CC but LA doesn't set CC */
   mvs_check_page (0, 4, 0);
   return \"LA	%0,%c2(,%1)\";
 }"
@@ -1983,7 +1983,7 @@ check_label_emit ();
   check_label_emit ();
   if ((unsigned) INTVAL (operands[2]) < 4096)
     {
-      CC_STATUS_INIT;  /* add assumes CC but LA doesnt set CC */
+      CC_STATUS_INIT;  /* add assumes CC but LA doesn't set CC */
       mvs_check_page (0, 4, 0);
       return \"LA	%0,%c2(,%1)\";
     }
@@ -2023,7 +2023,7 @@ check_label_emit ();
     {
       if (INTVAL (operands[2]) == -1)
 	{
-          CC_STATUS_INIT;  /* add assumes CC but BCTR doesnt set CC */
+          CC_STATUS_INIT;  /* add assumes CC but BCTR doesn't set CC */
 	  mvs_check_page (0, 2, 0);
 	  return \"BCTR	%0,0\";
 	}
@@ -2055,7 +2055,7 @@ check_label_emit ();
     {
       if (INTVAL (operands[2]) == -1)
 	{
-          CC_STATUS_INIT;  /* add assumes CC but BCTR doesnt set CC */
+          CC_STATUS_INIT;  /* add assumes CC but BCTR doesn't set CC */
 	  mvs_check_page (0, 2, 0);
 	  return \"BCTR	%0,0\";
 	}
@@ -2080,7 +2080,7 @@ check_label_emit ();
   "*
 {
   check_label_emit ();
-  CC_STATUS_INIT;  /* add assumes CC but LA doesnt set CC */
+  CC_STATUS_INIT;  /* add assumes CC but LA doesn't set CC */
   mvs_check_page (0, 4, 0);
   if (REG_P (operands[2]))
     return \"LA	%0,0(%1,%2)\";
@@ -2235,7 +2235,7 @@ check_label_emit ();
     }
   if (operands[2] == const1_rtx)
     {
-      CC_STATUS_INIT;  /* subtract assumes CC but BCTR doesnt set CC */
+      CC_STATUS_INIT;  /* subtract assumes CC but BCTR doesn't set CC */
       mvs_check_page (0, 2, 0);
       return \"BCTR	%0,0\";
     }
@@ -2264,7 +2264,7 @@ check_label_emit ();
     }
   if (operands[2] == const1_rtx)
     {
-      CC_STATUS_INIT;  /* subtract assumes CC but BCTR doesnt set CC */
+      CC_STATUS_INIT;  /* subtract assumes CC but BCTR doesn't set CC */
       mvs_check_page (0, 2, 0);
       return \"BCTR	%0,0\";
     }
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 39a55ad..8fe70a2 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1616,7 +1616,7 @@ classify_argument (mode, type, classes, bit_offset)
 	mode_alignment = 128;
       else if (mode == XCmode)
 	mode_alignment = 256;
-      /* Missalignmed fields are always returned in memory.  */
+      /* Misaligned fields are always returned in memory.  */
       if (bit_offset % mode_alignment)
 	return 0;
     }
@@ -1678,7 +1678,7 @@ classify_argument (mode, type, classes, bit_offset)
 }
 
 /* Examine the argument and return set number of register required in each
-   class.  Return 0 ifif parameter should be passed in memory.  */
+   class.  Return 0 iff parameter should be passed in memory.  */
 static int
 examine_argument (mode, type, in_return, int_nregs, sse_nregs)
      enum machine_mode mode;
@@ -2060,7 +2060,7 @@ ix86_function_value (valtype)
     return gen_rtx_REG (TYPE_MODE (valtype), VALUE_REGNO (TYPE_MODE (valtype)));
 }
 
-/* Return false ifif type is returned in memory.  */
+/* Return false iff type is returned in memory.  */
 int
 ix86_return_in_memory (type)
      tree type;
@@ -2853,7 +2853,7 @@ incdec_operand (op, mode)
      register rtx op;
      enum machine_mode mode ATTRIBUTE_UNUSED;
 {
-  /* On Pentium4, the inc and dec operations causes extra dependancy on flag
+  /* On Pentium4, the inc and dec operations causes extra dependency on flag
      registers, since carry flag is not set.  */
   if (TARGET_PENTIUM4 && !optimize_size)
     return 0;
@@ -4174,7 +4174,7 @@ ix86_expand_epilogue (style)
 	  }
       if (frame_pointer_needed)
 	{
-	  /* Leave results in shorter depdendancy chains on CPUs that are
+	  /* Leave results in shorter dependency chains on CPUs that are
 	     able to grok it fast.  */
 	  if (TARGET_USE_LEAVE)
 	    emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
@@ -9908,7 +9908,7 @@ ix86_flags_dependant (insn, dep_insn, insn_type)
   if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
     return 0;
 
-  /* This test is true if the dependant insn reads the flags but
+  /* This test is true if the dependent insn reads the flags but
      not any other potentially set register.  */
   if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
     return 0;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index fda3620..a23644a 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -167,7 +167,7 @@ extern int target_flags;
 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
 
 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
-   This mode wastes cache, but avoid missaligned data accesses and simplifies
+   This mode wastes cache, but avoid misaligned data accesses and simplifies
    address calculations.  */
 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 55175ca..5479fc1 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2363,7 +2363,7 @@
    (set_attr "mode" "DI")])
 
 ;; Convert impossible pushes of immediate to existing instructions.
-;; First try to get scratch register and go trought it.  In case this
+;; First try to get scratch register and go through it.  In case this
 ;; fails, push sign extended lower part first and then overwrite
 ;; upper part by 32bit move.
 (define_peephole2
@@ -2575,7 +2575,7 @@
    (set_attr "mode" "DI")])
 
 ;; Convert impossible stores of immediate to existing instructions.
-;; First try to get scratch register and go trought it.  In case this
+;; First try to get scratch register and go through it.  In case this
 ;; fails, move by 32bit parts.
 (define_peephole2
   [(match_scratch:DI 2 "r")
@@ -8106,7 +8106,7 @@
 		 (const_int 0)))]
   "TARGET_64BIT
    && ix86_match_ccmode (insn, CCNOmode)
-   /* The code bellow cannot deal with constants outside HOST_WIDE_INT.  */
+   /* The code below cannot deal with constants outside HOST_WIDE_INT.  */
    && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
    /* Ensure that resulting mask is zero or sign extended operand.  */
    && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
@@ -16198,7 +16198,7 @@
 
 ;; Misc patterns (?)
 
-;; This pattern exists to put a dependancy on all ebp-based memory accesses.
+;; This pattern exists to put a dependency on all ebp-based memory accesses.
 ;; Otherwise there will be nothing to keep
 ;; 
 ;; [(set (reg ebp) (reg esp))]
@@ -16904,7 +16904,7 @@
 ;; "and imm, reg" if reg dies.  The "and" form is also shorter (one
 ;; byte opcode instead of two, have a short form for byte operands),
 ;; so do it for other CPUs as well.  Given that the value was dead,
-;; this should not create any new dependancies.  Pass on the sub-word
+;; this should not create any new dependencies.  Pass on the sub-word
 ;; versions if we're concerned about partial register stalls.
 
 (define_peephole2
@@ -17147,12 +17147,12 @@
 ;; The ESP adjustments can be done by the push and pop instructions.  Resulting
 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes.  On
 ;; many CPUs it is also faster, since special hardware to avoid esp
-;; dependancies is present.
+;; dependencies is present.
 
 ;; While some of these converisons may be done using splitters, we use peepholes
 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
 
-;; Convert prologue esp substractions to push.
+;; Convert prologue esp subtractions to push.
 ;; We need register to push.  In order to keep verify_flow_info happy we have
 ;; two choices
 ;; - use scratch and clobber it in order to avoid dependencies
@@ -17184,7 +17184,7 @@
    (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
 	      (clobber (mem:BLK (scratch)))])])
 
-;; Convert esp substractions to push.
+;; Convert esp subtractions to push.
 (define_peephole2
   [(match_scratch:SI 0 "r")
    (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
@@ -17362,7 +17362,7 @@
    (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
 	      (clobber (mem:BLK (scratch)))])])
 
-;; Convert esp substractions to push.
+;; Convert esp subtractions to push.
 (define_peephole2
   [(match_scratch:DI 0 "r")
    (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
diff --git a/gcc/config/i386/xm-djgpp.h b/gcc/config/i386/xm-djgpp.h
index 2e5260e..b8367ac 100644
--- a/gcc/config/i386/xm-djgpp.h
+++ b/gcc/config/i386/xm-djgpp.h
@@ -30,7 +30,7 @@ Boston, MA 02111-1307, USA.  */
 /* Allow test for DOS drive names.  */
 #define HAVE_DOS_BASED_FILE_SYSTEM
 
-/* System dependant initialization for collect2
+/* System dependent initialization for collect2
    to tell system() to act like Unix.  */
 #define COLLECT2_HOST_INITIALIZATION \
   do { __system_flags |= (__system_allow_multiple_cmds			\
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index aef598b..87c35e7 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -1052,7 +1052,7 @@ ia64_split_timode (out, in, scratch)
 
    We got into problems in the first place by allowing a construct like
    (subreg:TF (reg:TI)), which we got from a union containing a long double.  
-   This solution attempts to prevent this situation from ocurring.  When
+   This solution attempts to prevent this situation from occurring.  When
    we see something like the above, we spill the inner register to memory.  */
 
 rtx
diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c
index 00d27e0..bb56125 100644
--- a/gcc/config/m68hc11/m68hc11.c
+++ b/gcc/config/m68hc11/m68hc11.c
@@ -4620,7 +4620,7 @@ m68hc11_z_replacement (insn)
     }
 
 
-  /* Replace all occurence of Z by replace_reg.
+  /* Replace all occurrence of Z by replace_reg.
      Stop when the last instruction to replace is reached.
      Also stop when we detect a change in the flow (but it's not
      necessary; just safeguard).  */
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index b2463f1..41cf9b2 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -7277,7 +7277,7 @@
       return \"bsr.l %0\";
 #else
       /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
-	 GAS just plain ignores it.  FIXME: not anymore, gas doesnt!  */
+	 GAS just plain ignores it.  FIXME: not anymore, gas doesn't!  */
       return \"jbsr %0,a1\";
 #endif
 #endif
@@ -7347,7 +7347,7 @@
       return \"bsr.l %1\";
 #else
       /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
-         GAS just plain ignores it.  FIXME: Not anymore, gas doesnt!  */
+         GAS just plain ignores it.  FIXME: Not anymore, gas doesn't!  */
       return \"jbsr %1,a1\";
 #endif
 #endif
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index 0b66920..1795a69 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -356,7 +356,7 @@ extern int mcore_stack_increment;
 #define LK_REG	15	/* overloaded on general register */
 #define AP_REG  16	/* fake arg pointer register */
 /* RBE: mcore.md depends on CC_REG being set to 17 */
-#define CC_REG	17	/* cant name it C_REG */
+#define CC_REG	17	/* can't name it C_REG */
 #define FP_REG  18	/* fake frame pointer register */
 
 /* Specify the registers used for certain standard purposes.
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index c378531..737f6c7 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -2505,7 +2505,7 @@ mmix_dbx_register_number (regno)
   return regno >= 224 ? (regno - 224) : (regno + 48);
 }
 
-/* End of target macro support funtions.
+/* End of target macro support functions.
 
    Now MMIX's own functions.  First the exported ones.  */
 
diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
index 373f78f..fb2cd4d 100644
--- a/gcc/config/ns32k/ns32k.h
+++ b/gcc/config/ns32k/ns32k.h
@@ -855,7 +855,7 @@ __transfer_from_trampoline ()		\
    because registers of CLASS are needed for spill registers.
 
    The default definition won't do because class LONG_FLOAT_REG0 has two
-   registers which are always acessed as a pair */
+   registers which are always accessed as a pair */
 
 #define CLASS_LIKELY_SPILLED_P(CLASS) \
   (reg_class_size[(int) (CLASS)] == 1 || (CLASS) == LONG_FLOAT_REG0)
diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md
index af1b60f..f7452ac 100644
--- a/gcc/config/ns32k/ns32k.md
+++ b/gcc/config/ns32k/ns32k.md
@@ -386,7 +386,7 @@
     }
   else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
     {
-	/* Must contain symbols so we don`t know how big it is. In
+	/* Must contain symbols so we don't know how big it is. In
 	 * that case addr might lead to overflow. For PIC symbolic
 	 * address loads always have to be done with addr.
 	 */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f10cef5a..56317af 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8318,7 +8318,7 @@ rs6000_select_section (decl, reloc)
    RELOC indicates whether the initial value of EXP requires
    link-time relocations.  If you do not define this macro, GCC will use
    the symbol name prefixed by `.' as the section name.  Note - this
-   macro can now be called for unitialised data items as well as
+   macro can now be called for uninitialized data items as well as
    initialised data and functions.  */
 
 void
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 882df2f..a6f79a1 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -582,7 +582,7 @@ fini_section ()								\
    RELOC indicates whether the initial value of EXP requires
    link-time relocations.  If you do not define this macro, GCC will use
    the symbol name prefixed by `.' as the section name.  Note - this
-   macro can now be called for unitialised data items as well as
+   macro can now be called for uninitialized data items as well as
    initialised data and functions.  */
 
 /* Override elfos.h definition.  */
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 69857c3..fd6a760 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -406,7 +406,7 @@
   [(const_int 1)])
 
 ;; arith3 insns are always pairable at the start, but not inecessarily at
-;; the end; however, there doesn;t seem to be a way to express that.
+;; the end; however, there doesn't seem to be a way to express that.
 (define_function_unit "single_issue"     1 0
   (and (eq_attr "issues" "2")
        (eq_attr "type" "arith3"))