builtins.c: Follow spelling conventions.

	* builtins.c: Follow spelling conventions.
	* cgraph.c: Likewise.
	* cpplex.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/iwmmxt.md: Likewise.
	* config/c4x/c4x-modes.def: Likewise.
	* config/c4x/c4x.c: Likewise.
	* config/c4x/c4x.h: Likewise.
	* config/c4x/c4x.md: Likewise.
	* config/i386/i386-interix.h: Likewise.
	* config/mips/mips.h: Likewise.

From-SVN: r68648

8 files changed, 12 insertions, 12 deletions

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c0ee99e..c02e7be 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2094,7 +2094,7 @@ arm_va_arg (tree valist, tree type)
       TREE_SIDE_EFFECTS (t) = 1;
       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
 
-      /* This is to stop the combine pass optimising
+      /* This is to stop the combine pass optimizing
 	 away the alignment adjustment.  */
       mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
     }
diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md
index 5f3fd7b..f9ef521 100644
--- a/gcc/config/arm/iwmmxt.md
+++ b/gcc/config/arm/iwmmxt.md
@@ -185,7 +185,7 @@
    (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])
 
 ;; This pattern should not be needed.  It is to match a
-;; wierd case generated by GCC when no optimisations are
+;; wierd case generated by GCC when no optimizations are
 ;; enabled.  (Try compiling gcc/testsuite/gcc.c-torture/
 ;; compile/simd-5.c at -O0).  The mode for operands[1] is
 ;; deliberately omitted.
diff --git a/gcc/config/c4x/c4x-modes.def b/gcc/config/c4x/c4x-modes.def
index 5079806..be536e0 100644
--- a/gcc/config/c4x/c4x-modes.def
+++ b/gcc/config/c4x/c4x-modes.def
@@ -25,7 +25,7 @@
 
    On the C4x, we have a "no-overflow" mode which is used when an ADD,
    SUB, NEG, or MPY insn is used to set the condition code.  This is
-   to prevent the combiner from optimising away a following CMP of the
+   to prevent the combiner from optimizing away a following CMP of the
    result with zero when a signed conditional branch or load insn
    follows.
 
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index 5d097cc..bc67783 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -1692,7 +1692,7 @@ c4x_legitimize_address (orig, mode)
 
 /* Provide the costs of an addressing mode that contains ADDR.
    If ADDR is not a valid address, its cost is irrelevant.  
-   This is used in cse and loop optimisation to determine
+   This is used in cse and loop optimization to determine
    if it is worthwhile storing a common address into a register. 
    Unfortunately, the C4x address cost depends on other operands.  */
 
@@ -2437,7 +2437,7 @@ c4x_rptb_insert (insn)
 
 /* We need to use direct addressing for large constants and addresses
    that cannot fit within an instruction.  We must check for these
-   after after the final jump optimisation pass, since this may
+   after after the final jump optimization pass, since this may
    introduce a local_move insn for a SYMBOL_REF.  This pass
    must come before delayed branch slot filling since it can generate
    additional instructions.
@@ -3642,7 +3642,7 @@ c4x_address_conflict (op0, op1, store0, store1)
 	 cause problems except when writing to a hardware device such
 	 as a FIFO since the second write will be lost.  The user
 	 should flag the hardware location as being volatile so that
-	 we don't do this optimisation.  While it is unlikely that we
+	 we don't do this optimization.  While it is unlikely that we
 	 have an aliased address if both locations are not marked
 	 volatile, it is probably safer to flag a potential conflict
 	 if either location is volatile.  */
@@ -4034,7 +4034,7 @@ legitimize_operands (code, operands, mode)
       /* During RTL generation, force constants into pseudos so that
 	 they can get hoisted out of loops.  This will tie up an extra
 	 register but can save an extra cycle.  Only do this if loop
-	 optimisation enabled.  (We cannot pull this trick for add and
+	 optimization enabled.  (We cannot pull this trick for add and
 	 sub instructions since the flow pass won't find
 	 autoincrements etc.)  This allows us to generate compare
 	 instructions like CMPI R0, *AR0++ where R0 = 42, say, instead
diff --git a/gcc/config/c4x/c4x.h b/gcc/config/c4x/c4x.h
index fb3622b..3fa2d91 100644
--- a/gcc/config/c4x/c4x.h
+++ b/gcc/config/c4x/c4x.h
@@ -775,7 +775,7 @@ enum reg_class
    is defined since the MPY|ADD insns require the classes R0R1_REGS and
    R2R3_REGS which are used by the function return registers (R0,R1) and
    the register arguments (R2,R3), respectively.  I'm reluctant to define
-   this macro since it stomps on many potential optimisations.  Ideally
+   this macro since it stomps on many potential optimizations.  Ideally
    it should have a register class argument so that not all the register
    classes gets penalised for the sake of a naughty few...  For long
    double arithmetic we need two additional registers that we can use as
diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md
index 07e140b..0957fe9 100644
--- a/gcc/config/c4x/c4x.md
+++ b/gcc/config/c4x/c4x.md
@@ -3127,9 +3127,9 @@
 ; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best
 ; thing would be to get the small constant loaded into a register (say r0)
 ; so that it could be hoisted out of the loop so that we only
-; would need to do cmpi3 *ar0++, r0.  Now the loop optimisation pass
+; would need to do cmpi3 *ar0++, r0.  Now the loop optimization pass
 ; comes before the flow pass (which finds autoincrements) so we're stuck.
-; Ideally, GCC requires another loop optimisation pass (preferably after
+; Ideally, GCC requires another loop optimization pass (preferably after
 ; reload) so that it can hoist invariants out of loops.
 ; The current solution modifies legitimize_operands () so that small
 ; constants are forced into a pseudo register.
diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h
index c58d07b..4d5e202 100644
--- a/gcc/config/i386/i386-interix.h
+++ b/gcc/config/i386/i386-interix.h
@@ -236,7 +236,7 @@ Boston, MA 02111-1307, USA.  */
 #define TARGET_NOP_FUN_DLLIMPORT 1
 #define drectve_section()  /* nothing */
 
-/* Objective C has its own packing rules...
+/* Objective-C has its own packing rules...
    Objc tries to parallel the code in stor-layout.c at runtime	
    (see libobjc/encoding.c).  This (compile-time) packing info isn't 
    available at runtime, so it's hopeless to try.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 40ea4df..6325d95 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3166,7 +3166,7 @@ typedef struct mips_args {
 
 
 /* The cost of loading values from the constant pool.  It should be
-   larger than the cost of any constant we want to synthesise in-line.  */
+   larger than the cost of any constant we want to synthesize in-line.  */
 
 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)