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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-10-27 20:42:30 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-02 20:07:08 +0100 |
| commit | a1a6b912b5f905e768da4d0f434591b4d523be49 (patch) | |
| tree | 79ccfa98309b43376978f0b56caf46197f6cd16f /gcc/config | |
| parent | abaa32c7384edef065c79741764bc112dd18f32d (diff) | |
| download | gcc-a1a6b912b5f905e768da4d0f434591b4d523be49.zip gcc-a1a6b912b5f905e768da4d0f434591b4d523be49.tar.gz gcc-a1a6b912b5f905e768da4d0f434591b4d523be49.tar.bz2 | |
RISC-V: Add Zawrs ISA extension support
This patch adds support for the Zawrs ISA extension.
Zawrs has been ratified by the RISC-V BoD on Oct 20th, 2022.
Binutils support has been merged as:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=eb668e50036e979fb0a74821df4eee0307b44e66
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zawrs extension.
* config/riscv/riscv-opts.h (MASK_ZAWRS): New.
(TARGET_ZAWRS): New.
* config/riscv/riscv.opt: New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zawrs.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv-opts.h | 3 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 1dfe8c8..25fd85b 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -73,6 +73,9 @@ enum stack_protector_guard { #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) +#define MASK_ZAWRS (1 << 0) +#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) + #define MASK_ZBA (1 << 0) #define MASK_ZBB (1 << 1) #define MASK_ZBC (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 426ea95..7c3ca48 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -204,6 +204,9 @@ TargetVariable int riscv_zi_subext TargetVariable +int riscv_za_subext + +TargetVariable int riscv_zb_subext TargetVariable |