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| author | liuhongt <hongtao.liu@intel.com> | 2021-09-28 12:55:10 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-10-08 10:09:51 +0800 |
| commit | 77ca2cfcdcccee3c8e8aeaf1d03e9920893d2486 (patch) | |
| tree | 5a13d925dac18a081d831f7b49f2a349d053898b /gcc/config | |
| parent | 2b8453c401b699ed93c085d0413ab4b5030bcdb8 (diff) | |
| download | gcc-77ca2cfcdcccee3c8e8aeaf1d03e9920893d2486.zip gcc-77ca2cfcdcccee3c8e8aeaf1d03e9920893d2486.tar.gz gcc-77ca2cfcdcccee3c8e8aeaf1d03e9920893d2486.tar.bz2 | |
Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.
gcc/ChangeLog:
PR target/102494
* config/i386/i386-expand.c (emit_reduc_half): Hanlde V4HImode.
* config/i386/mmx.md (reduc_plus_scal_v4hi): New.
(reduc_<code>_scal_v4hi): New.
gcc/testsuite/ChangeLog:
* gcc.target/i386/mmx-reduce-op-1.c: New test.
* gcc.target/i386/mmx-reduce-op-2.c: New test.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386-expand.c | 5 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 36 |
2 files changed, 41 insertions, 0 deletions
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 4780b99..3e6f7d8e 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -16043,6 +16043,11 @@ emit_reduc_half (rtx dest, rtx src, int i) case E_V2DFmode: tem = gen_vec_interleave_highv2df (dest, src, src); break; + case E_V4HImode: + d = gen_reg_rtx (V1DImode); + tem = gen_mmx_lshrv1di3 (d, gen_lowpart (V1DImode, src), + GEN_INT (i / 2)); + break; case E_V16QImode: case E_V8HImode: case E_V8HFmode: diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index c9467bc..106d41c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -3965,6 +3965,42 @@ DONE; }) +(define_expand "reduc_plus_scal_v4hi" + [(plus:V4HI + (match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand"))] + "TARGET_MMX_WITH_SSE" +{ + rtx tmp = gen_reg_rtx (V4HImode); + ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx)); + DONE; +}) + +(define_expand "reduc_<code>_scal_v4hi" + [(smaxmin:V4HI + (match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand"))] + "TARGET_MMX_WITH_SSE" +{ + rtx tmp = gen_reg_rtx (V4HImode); + ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx)); + DONE; +}) + +(define_expand "reduc_<code>_scal_v4hi" + [(umaxmin:V4HI + (match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand"))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1" +{ + rtx tmp = gen_reg_rtx (V4HImode); + ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx)); + DONE; +}) + (define_expand "usadv8qi" [(match_operand:V2SI 0 "register_operand") (match_operand:V8QI 1 "register_operand") |