c-typeck.c, [...]: Fix comment typos and formatting.

	* c-typeck.c, combine.c, cse.c, dominance.c, et-forest.h,
	ggc-page.c, var-tracking.c, config/fp-bit.c, config/c4x/c4x.c,
	config/cris/cris.c, config/i386/ppro.md, config/i860/i860.c,
	config/i860/i860.h, config/m32r/m32r.h, config/m32r/xm-m32r.h,
	config/m68hc11/m68hc11.h, config/m68hc11/m68hc11.md,
	config/mips/mips.c, config/mmix/mmix.c, config/ns32k/ns32k.h,
	config/pa/pa.c, config/pa/pa32-regs.h, config/pa/pa64-regs.h,
	config/pdp11/pdp11.h, config/rs6000/rs6000.c,
	config/stormy16/stormy16.c: Fix comment typos and formatting.

From-SVN: r79303

19 files changed, 38 insertions, 38 deletions

diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index 7892047..7500526 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -766,7 +766,7 @@ c4x_leaf_function_p (void)
      to save/restore the registers we actually use.
      For the global variable leaf_function to be set, we need
      to define LEAF_REGISTERS and all that it entails.
-     Let's check ourselves...   */
+     Let's check ourselves....  */
 
   if (lookup_attribute ("leaf_pretend",
 			TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
@@ -929,7 +929,7 @@ c4x_expand_prologue (void)
 	}
       else
 	{
-	  /* If we use ar3, we need to push it.   */
+	  /* If we use ar3, we need to push it.  */
 	  dont_push_ar3 = 0;
 	  if ((size != 0) || (current_function_args_size != 0))
 	    {
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index b5568d6..86795af 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -462,7 +462,7 @@ cris_mem_call_operand (rtx op, enum machine_mode mode)
   return cris_general_operand_or_symbol (xmem, GET_MODE (op));
 }
 
-/* The CONDITIONAL_REGISTER_USAGE worker.   */
+/* The CONDITIONAL_REGISTER_USAGE worker.  */
 
 void
 cris_conditional_register_usage (void)
diff --git a/gcc/config/fp-bit.c b/gcc/config/fp-bit.c
index 0de191d..748e24b 100644
--- a/gcc/config/fp-bit.c
+++ b/gcc/config/fp-bit.c
@@ -915,7 +915,7 @@ _fpmul_parts ( fp_number_type *  a,
 	{
 	  /* We're a further than half way by a small amount corresponding
 	     to the bits set in "low".  Knowing that, we round here and
-	     not in pack_d, because there we don't have "low" avaliable
+	     not in pack_d, because there we don't have "low" available
 	     anymore.  */
 	  high += GARDROUND + 1;
 
@@ -1034,7 +1034,7 @@ _fpdiv_parts (fp_number_type * a,
 	    /* We're a further than half way by the small amount
 	       corresponding to the bits set in "numerator".  Knowing
 	       that, we round here and not in pack_d, because there we
-	       don't have "numerator" avaliable anymore.  */
+	       don't have "numerator" available anymore.  */
 	    quotient += GARDROUND + 1;
 
 	    /* Avoid further rounding in pack_d.  */
diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md
index fc1374d..c8bd5b4 100644
--- a/gcc/config/i386/ppro.md
+++ b/gcc/config/i386/ppro.md
@@ -18,7 +18,7 @@
 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
 ;; Boston, MA 02111-1307, USA.  */
 
-;; The P6 familiy includes the Pentium Pro, Pentium II, Pentium III, Celeron
+;; The P6 family includes the Pentium Pro, Pentium II, Pentium III, Celeron
 ;; and Xeon lines of CPUs.  The DFA scheduler description in this file is
 ;; based on information that can be found in the following three documents:
 ;;
@@ -111,7 +111,7 @@
 ;; P3FPU
 ;;
 ;; (SAC=Store Address Calculation, SDA=Store Data Unit, P3FPU = SSE unit,
-;;  JUE = Jump Execution Unit, AGU = Addres Generation Unit)
+;;  JUE = Jump Execution Unit, AGU = Address Generation Unit)
 ;;
 (define_cpu_unit "p0,p1" "ppro_core")
 (define_cpu_unit "p2" "ppro_load")
@@ -135,7 +135,7 @@
 ;; doesn't make sense because we don't know how these instructions are
 ;; executed in the core.  So we just model that they can only be decoded
 ;; on decoder 0, and say that it takes a little while before the result
-;; is availale.
+;; is available.
 (define_insn_reservation "ppro_complex_insn" 6
 			 (eq_attr "type" "other,multi,call,callv,str")
 			 "decoder0")
@@ -200,14 +200,14 @@
 			      (eq_attr "type" "cld"))
 			 "decoder0,(p0+p1)*2")
 
-;; The P6 has a sophisticated branch prediction mechanism to miminize
+;; The P6 has a sophisticated branch prediction mechanism to minimize
 ;; latencies due to branching.  In particular, it has a fast way to
 ;; execute branches that are taken multiple times (such as in loops).
 ;; Branches not taken suffer no penalty, and correctly predicted
 ;; branches cost only one fetch cycle.  Mispredicted branches are very
 ;; costly: typically 15 cycles and possibly as many as 26 cycles.
 ;;
-;; Unfortunatetely all this makes it quite difficult to properly model
+;; Unfortunately all this makes it quite difficult to properly model
 ;; the latencies for the compiler.  Here I've made the choice to be
 ;; optimistic and assume branches are often predicted correctly, so
 ;; they have latency 1, and the decoders are not blocked.
diff --git a/gcc/config/i860/i860.c b/gcc/config/i860/i860.c
index 1ee9e4e..7c455eb 100644
--- a/gcc/config/i860/i860.c
+++ b/gcc/config/i860/i860.c
@@ -159,7 +159,7 @@ reg_clobbered_p (rtx reg, rtx in)
 	  /* Anything that sets just part of the register
 	     is considered using as well as setting it.
 	     But note that a straight SUBREG of a single-word value
-	     clobbers the entire value.   */
+	     clobbers the entire value.  */
 	  if (dest != SET_DEST (in)
 	      && ! (GET_CODE (SET_DEST (in)) == SUBREG
 		    || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
@@ -766,7 +766,7 @@ load_opcode (enum machine_mode mode, const char *args, rtx reg)
 /* Return a template for a store instruction with mode MODE and
    arguments from the string ARGS.
 
-   This string is in static storage.   */
+   This string is in static storage.  */
 
 static const char *
 store_opcode (enum machine_mode mode, const char *args, rtx reg)
diff --git a/gcc/config/i860/i860.h b/gcc/config/i860/i860.h
index 1b29a08..6e451e5 100644
--- a/gcc/config/i860/i860.h
+++ b/gcc/config/i860/i860.h
@@ -271,7 +271,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
-/* Give names of register classes as strings for dump file.   */
+/* Give names of register classes as strings for dump file.  */
 
 #define REG_CLASS_NAMES \
  {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 5b71611..f2574ac 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -737,7 +737,7 @@ enum reg_class
 
 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
 
-/* Give names of register classes as strings for dump file.   */
+/* Give names of register classes as strings for dump file.  */
 #define REG_CLASS_NAMES \
   { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
 
@@ -1764,7 +1764,7 @@ extern char m32r_punct_chars[256];
 extern struct rtx_def * m32r_compare_op0;
 extern struct rtx_def * m32r_compare_op1;
 
-/* M32R function types.   */
+/* M32R function types.  */
 enum m32r_function_type
 {
   M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
diff --git a/gcc/config/m32r/xm-m32r.h b/gcc/config/m32r/xm-m32r.h
index 5859449..a06ad8a 100644
--- a/gcc/config/m32r/xm-m32r.h
+++ b/gcc/config/m32r/xm-m32r.h
@@ -30,7 +30,7 @@
 #define HOST_WORDS_BIG_ENDIAN    1
 
 /* target machine dependencies.
-   tm.h is a symbolic link to the actual target specific file.   */
+   tm.h is a symbolic link to the actual target specific file.  */
 #include "tm.h"
 
 /* Arguments to use with `exit'.  */
diff --git a/gcc/config/m68hc11/m68hc11.h b/gcc/config/m68hc11/m68hc11.h
index 4dee106..8dfd83f 100644
--- a/gcc/config/m68hc11/m68hc11.h
+++ b/gcc/config/m68hc11/m68hc11.h
@@ -1599,7 +1599,7 @@ do {                                                                    \
    sections when it shrinks the code.  This results in invalid addresses
    when debugging.  This does not bless too much the HC11/HC12 as most
    applications are embedded and small, hence a reasonable debug info.
-   This problem is known for binutils 2.13, 2.14 and mainline.   */
+   This problem is known for binutils 2.13, 2.14 and mainline.  */
 #undef HAVE_AS_DWARF2_DEBUG_LINE
 
 /* The prefix for local labels.  You should be able to define this as
diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index 5e6bc23..71c45ff 100644
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -7204,7 +7204,7 @@
 
 ;;
 ;; Remove one load when copying a value to/from memory and also
-;; to a register.  Take care not cloberring a possible register used
+;; to a register.  Take care not clobbering a possible register used
 ;; by operand 2.
 ;; Replace: "ldd 0,y; std 2,y; ldx 0,y" into "ldx 0,y; stx 2,y"
 ;;
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 037a25a..c99053b 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3904,7 +3904,7 @@ mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
 	  int off, i;
 
 	  /* Set OFF to the offset from virtual_incoming_args_rtx of
-	     the first float register.   The FP save area lies below
+	     the first float register.  The FP save area lies below
 	     the integer one, and is aligned to UNITS_PER_FPVALUE bytes.  */
 	  off = -gp_saved * UNITS_PER_WORD;
 	  off &= ~(UNITS_PER_FPVALUE - 1);
@@ -5976,7 +5976,7 @@ mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
 				 unsigned int align)
 {
   /* If the target wants uninitialized const declarations in
-     .rdata then don't put them in .comm.   */
+     .rdata then don't put them in .comm.  */
   if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
       && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
       && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
@@ -7019,7 +7019,7 @@ mips_expand_epilogue (int sibcall_p)
 			      stack_pointer_rtx,
 			      GEN_INT (step2)));
 
-  /* Add in the __builtin_eh_return stack adjustment.   We need to
+  /* Add in the __builtin_eh_return stack adjustment.  We need to
      use a temporary in mips16 code.  */
   if (current_function_calls_eh_return)
     {
@@ -9189,7 +9189,7 @@ mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
    the division is not immediately followed by a shift[1][2].  We also
    need to stop the division from being put into a branch delay slot[3].
    The easiest way to avoid both problems is to add a nop after the
-   division.  When a divide-by-zero check is neeeded, this nop can be
+   division.  When a divide-by-zero check is needed, this nop can be
    used to fill the branch delay slot.
 
    [1] If a double-word or a variable shift executes immediately
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index 4d239dd..8bf8e0e 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -838,7 +838,7 @@ mmix_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_farp,
     *pretend_sizep = (MMIX_MAX_ARGS_IN_REGS - (args_so_farp->regs + 1)) * 8;
 
   /* We assume that one argument takes up one register here.  That should
-     be true until we start messing with multi-reg parameters.   */
+     be true until we start messing with multi-reg parameters.  */
   if ((7 + (MMIX_FUNCTION_ARG_SIZE (mode, vartype))) / 8 != 1)
     internal_error ("MMIX Internal: Last named vararg would not fit in a register");
 }
diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
index f42fde0..0730a5f 100644
--- a/gcc/config/ns32k/ns32k.h
+++ b/gcc/config/ns32k/ns32k.h
@@ -433,7 +433,7 @@ enum reg_class
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
-/* Give names of register classes as strings for dump file.   */
+/* Give names of register classes as strings for dump file.  */
 
 #define REG_CLASS_NAMES							    \
  {"NO_REGS", "GENERAL_REGS", "FLOAT_REG0", "LONG_FLOAT_REG0", "FLOAT_REGS", \
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 6c6fe04..d9dea93 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1508,7 +1508,7 @@ emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
      We have to do this because the REG_POINTER flag is not correctly
      carried through various optimization passes and CSE may substitute
      a pseudo without the pointer set for one with the pointer set.  As
-     a result, we loose various opportunites to create insns with
+     a result, we loose various opportunities to create insns with
      unscaled indexed addresses.  */
   if (!TARGET_NO_SPACE_REGS
       && !cse_not_expected
@@ -2192,7 +2192,7 @@ read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
 
 
 /* Return the best assembler insn template
-   for moving operands[1] into operands[0] as a fullword.   */
+   for moving operands[1] into operands[0] as a fullword.  */
 const char *
 singlemove_string (rtx *operands)
 {
@@ -2655,7 +2655,7 @@ find_addr_reg (rtx addr)
    OPERANDS[3] is a register for temporary storage.
    OPERANDS[4] is the size as a CONST_INT
    OPERANDS[5] is the alignment safe to use, as a CONST_INT.
-   OPERANDS[6] is another temporary register.   */
+   OPERANDS[6] is another temporary register.  */
 
 const char *
 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
@@ -3142,7 +3142,7 @@ output_ascii (FILE *file, const char *p, int size)
 {
   int i;
   int chars_output;
-  unsigned char partial_output[16];	/* Max space 4 chars can occupy.   */
+  unsigned char partial_output[16];	/* Max space 4 chars can occupy.  */
 
   /* The HP assembler can only take strings of 256 characters at one
      time.  This is a limitation on input line length, *not* the
@@ -6725,7 +6725,7 @@ output_dbra (rtx *operands, rtx insn, int which_alternative)
   else
     {
       /* Reload loop counter from memory, the store back to memory
-	 happens in the branch's delay slot.   */
+	 happens in the branch's delay slot.  */
       output_asm_insn ("ldw %0,%4", operands);
       if (get_attr_length (insn) == 12)
 	return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
@@ -6828,7 +6828,7 @@ output_movb (rtx *operands, rtx insn, int which_alternative,
   else if (which_alternative == 2)
     {
       /* Reload loop counter from memory, the store back to memory
-	 happens in the branch's delay slot.   */
+	 happens in the branch's delay slot.  */
       if (get_attr_length (insn) == 8)
 	return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
       else
diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index ac23a69..3a51324 100644
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -228,7 +228,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
-/* Give names of register classes as strings for dump file.   */
+/* Give names of register classes as strings for dump file.  */
 
 #define REG_CLASS_NAMES \
   {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
@@ -262,7 +262,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
    : SHIFT_REGS)
 
 /* Get reg_class from a letter such as appears in the machine description.  */
-/* Keep 'x' for backward compatibility with user asm.   */
+/* Keep 'x' for backward compatibility with user asm.  */
 #define REG_CLASS_FROM_LETTER(C) \
   ((C) == 'f' ? FP_REGS :					\
    (C) == 'y' ? FPUPPER_REGS :					\
diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h
index 29cc230..b139777 100644
--- a/gcc/config/pa/pa64-regs.h
+++ b/gcc/config/pa/pa64-regs.h
@@ -211,7 +211,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
-/* Give names of register classes as strings for dump file.   */
+/* Give names of register classes as strings for dump file.  */
 
 #define REG_CLASS_NAMES \
   {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
@@ -257,7 +257,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
 
 
 /* Get reg_class from a letter such as appears in the machine description.  */
-/* Keep 'x' for backward compatibility with user asm.   */
+/* Keep 'x' for backward compatibility with user asm.  */
 #define REG_CLASS_FROM_LETTER(C) \
   ((C) == 'f' ? FP_REGS :					\
    (C) == 'y' ? FP_REGS :					\
diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h
index 568a0ad..5e36042 100644
--- a/gcc/config/pdp11/pdp11.h
+++ b/gcc/config/pdp11/pdp11.h
@@ -390,7 +390,7 @@ enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REG
 
 /* #define GENERAL_REGS ALL_REGS */
 
-/* Give names of register classes as strings for dump file.   */
+/* Give names of register classes as strings for dump file.  */
 
 #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" }
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 3e4aeb8..6ed984c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2349,7 +2349,7 @@ rs6000_special_round_type_align (tree type, int computed, int specified)
   tree field = TYPE_FIELDS (type);
 
   /* Skip all the static variables only if ABI is greater than
-     1 or equal to 0.   */
+     1 or equal to 0.  */
   while (field != NULL && TREE_CODE (field) == VAR_DECL)
     field = TREE_CHAIN (field);
 
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index e19236b..9ba54c1 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -1489,7 +1489,7 @@ xstormy16_asm_out_destructor (rtx symbol, int priority)
   const char *section = ".dtors";
   char buf[16];
 
-  /* ??? This only works reliably with the GNU linker.   */
+  /* ??? This only works reliably with the GNU linker.  */
   if (priority != DEFAULT_INIT_PRIORITY)
     {
       sprintf (buf, ".dtors.%.5u",
@@ -1511,7 +1511,7 @@ xstormy16_asm_out_constructor (rtx symbol, int priority)
   const char *section = ".ctors";
   char buf[16];
 
-  /* ??? This only works reliably with the GNU linker.   */
+  /* ??? This only works reliably with the GNU linker.  */
   if (priority != DEFAULT_INIT_PRIORITY)
     {
       sprintf (buf, ".ctors.%.5u",