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| author | Richard Sandiford <richard.sandiford@arm.com> | 2022-10-20 10:37:33 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2022-10-20 10:37:33 +0100 |
| commit | 57675c7f92a3bd3ca8dae1faac7f2f51d40e0f9e (patch) | |
| tree | 4d3cda0f39a73292bc96f0071693a4a2eb758b3d /gcc/config | |
| parent | 6bec66640597e2604f51fc1642c7d279164cd442 (diff) | |
| download | gcc-57675c7f92a3bd3ca8dae1faac7f2f51d40e0f9e.zip gcc-57675c7f92a3bd3ca8dae1faac7f2f51d40e0f9e.tar.gz gcc-57675c7f92a3bd3ca8dae1faac7f2f51d40e0f9e.tar.bz2 | |
aarch64: Prevent generation of /M BRKAS and BRKBS
Bit of a brown-paper-bag bug, but: GCC was generating
non-existent merging forms of BRKAS and BRKBS. Those
instructions only support zero predication (although
BRKA and BRKB support both).
gcc/
* config/aarch64/aarch64-sve.md (*aarch64_brk<brk_op>_cc): Remove
merging alternative.
(*aarch64_brk<brk_op>_ptest): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/brka_1.c: Expect a separate
PTEST instruction.
* gcc.target/aarch64/sve/acle/general/brkb_1.c: Likewise.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index e2bb802..b8cc47e 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -9612,45 +9612,41 @@ (define_insn "*aarch64_brk<brk_op>_cc" [(set (reg:CC_NZC CC_REGNUM) (unspec:CC_NZC - [(match_operand:VNx16BI 1 "register_operand" "Upa, Upa") + [(match_operand:VNx16BI 1 "register_operand" "Upa") (match_dup 1) (match_operand:SI 4 "aarch64_sve_ptrue_flag") (unspec:VNx16BI [(match_dup 1) - (match_operand:VNx16BI 2 "register_operand" "Upa, Upa") - (match_operand:VNx16BI 3 "aarch64_simd_reg_or_zero" "Dz, 0")] + (match_operand:VNx16BI 2 "register_operand" "Upa") + (match_operand:VNx16BI 3 "aarch64_simd_imm_zero")] SVE_BRK_UNARY)] UNSPEC_PTEST)) - (set (match_operand:VNx16BI 0 "register_operand" "=Upa, Upa") + (set (match_operand:VNx16BI 0 "register_operand" "=Upa") (unspec:VNx16BI [(match_dup 1) (match_dup 2) (match_dup 3)] SVE_BRK_UNARY))] "TARGET_SVE" - "@ - brk<brk_op>s\t%0.b, %1/z, %2.b - brk<brk_op>s\t%0.b, %1/m, %2.b" + "brk<brk_op>s\t%0.b, %1/z, %2.b" ) ;; Same, but with only the flags result being interesting. (define_insn "*aarch64_brk<brk_op>_ptest" [(set (reg:CC_NZC CC_REGNUM) (unspec:CC_NZC - [(match_operand:VNx16BI 1 "register_operand" "Upa, Upa") + [(match_operand:VNx16BI 1 "register_operand" "Upa") (match_dup 1) (match_operand:SI 4 "aarch64_sve_ptrue_flag") (unspec:VNx16BI [(match_dup 1) - (match_operand:VNx16BI 2 "register_operand" "Upa, Upa") - (match_operand:VNx16BI 3 "aarch64_simd_reg_or_zero" "Dz, 0")] + (match_operand:VNx16BI 2 "register_operand" "Upa") + (match_operand:VNx16BI 3 "aarch64_simd_imm_zero")] SVE_BRK_UNARY)] UNSPEC_PTEST)) - (clobber (match_scratch:VNx16BI 0 "=Upa, Upa"))] + (clobber (match_scratch:VNx16BI 0 "=Upa"))] "TARGET_SVE" - "@ - brk<brk_op>s\t%0.b, %1/z, %2.b - brk<brk_op>s\t%0.b, %1/m, %2.b" + "brk<brk_op>s\t%0.b, %1/z, %2.b" ) ;; ------------------------------------------------------------------------- |