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| author | Andrew Pinski <apinski@cavium.com> | 2016-09-12 21:30:33 +0000 |
|---|---|---|
| committer | Andrew Pinski <pinskia@gcc.gnu.org> | 2016-09-12 14:30:33 -0700 |
| commit | 54700e2e7f11d6715670182ee37a378a89d77a12 (patch) | |
| tree | 6e800cf87fc5a29de7310822ed32aaedcc3b58ca /gcc/config | |
| parent | 47f138d178c2b89b0f9f964404bb15243cd72a28 (diff) | |
| download | gcc-54700e2e7f11d6715670182ee37a378a89d77a12.zip gcc-54700e2e7f11d6715670182ee37a378a89d77a12.tar.gz gcc-54700e2e7f11d6715670182ee37a378a89d77a12.tar.bz2 | |
Add tunning of ldpw for THunderX.
2016-09-12 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-tuning-flags.def (SLOW_UNALIGNED_LDPW):
New tuning option.
* config/aarch64/aarch64.c (thunderx_tunings): Enable
AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW.
(aarch64_operands_ok_for_ldpstp): Return false if
AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW and the mode
was SImode and the alignment is less than 8 byte.
(aarch64_operands_adjust_ok_for_ldpstp): Likewise.
2016-09-12 Andrew Pinski <apinski@cavium.com>
* gcc.target/aarch64/thunderxloadpair.c: New testcase.
* gcc.target/aarch64/thunderxnoloadpair.c: New testcase.
From-SVN: r240102
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-tuning-flags.def | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 20 |
2 files changed, 24 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index 048c2a3..68b5ba0 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -29,3 +29,8 @@ AARCH64_TUNE_ to give an enum name. */ AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS) + +/* Don't create non-8 byte aligned load/store pair. That is if the +two load/stores are not at least 8 byte aligned don't create load/store +pairs. */ +AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 2be750e..3fcfaa8 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -712,7 +712,7 @@ static const struct tune_params thunderx_tunings = 0, /* max_case_values. */ 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) /* tune_flags. */ }; static const struct tune_params xgene1_tunings = @@ -13629,6 +13629,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load, if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2)) return false; + /* If we have SImode and slow unaligned ldp, + check the alignment to be at least 8 byte. */ + if (mode == SImode + && (aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) + && !optimize_size + && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + return false; + /* Check if the addresses are in the form of [base+offset]. */ extract_base_offset_in_addr (mem_1, &base_1, &offset_1); if (base_1 == NULL_RTX || offset_1 == NULL_RTX) @@ -13788,6 +13797,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load, return false; } + /* If we have SImode and slow unaligned ldp, + check the alignment to be at least 8 byte. */ + if (mode == SImode + && (aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) + && !optimize_size + && MEM_ALIGN (mem_1) < 8 * BITS_PER_UNIT) + return false; + if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1))) rclass_1 = FP_REGS; else |