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| author | Jeff Law <jeffreyalaw@gmail.com> | 2022-10-17 19:19:25 -0400 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2022-10-17 19:19:25 -0400 |
| commit | 43ee3f64cb519f2675fa1771007d4aa3baba944f (patch) | |
| tree | 933db053eba2660c6603939066e00c6d32833dac /gcc/config | |
| parent | 9072db9d5b549db5e2f14335ac0adc7735d43bc6 (diff) | |
| download | gcc-43ee3f64cb519f2675fa1771007d4aa3baba944f.zip gcc-43ee3f64cb519f2675fa1771007d4aa3baba944f.tar.gz gcc-43ee3f64cb519f2675fa1771007d4aa3baba944f.tar.bz2 | |
Add missing splitter for H8
While testing a minor optimization on the H8 my builds failed due to
failure to split a zero-extended memory load. That particular pattern
is a bit special on the H8 in that it's split at assembly time primarily
to get the length computations correct. Arguably that alternative should
go away completely, but I haven't really looked into that.
Anyway, with the final-asm split we obviously need to match a define_split
somewhere. But none was ever written after adding CCZN optimizations. So
if we had a zero extend of a memory operand and it was used to eliminate
a compare, then we'd abort at final asm time.
Regression tested (in conjunction with various other in-progress patches) on
H8 without regressions.
gcc/
* config/h8300/extensions.md (CCZN setting zero extended load): Add
missing splitter.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/h8300/extensions.md | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/gcc/config/h8300/extensions.md b/gcc/config/h8300/extensions.md index 74647c7..7149dc0 100644 --- a/gcc/config/h8300/extensions.md +++ b/gcc/config/h8300/extensions.md @@ -47,6 +47,24 @@ operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); }) +;; Similarly, but setting cczn. +(define_split + [(set (reg:CCZN CC_REG) + (compare:CCZN + (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")) + (const_int 0))) + (set (match_operand:HI 0 "register_operand" "") + (zero_extend:HI (match_dup 1)))] + "!REG_P (operands[1]) && reload_completed" + [(parallel [(set (match_dup 2) (match_dup 1)) + (clobber (reg:CC CC_REG))]) + (parallel [(set (reg:CCZN CC_REG) + (compare:CCZN (zero_extend:HI (match_dup 2)) (const_int 0))) + (set (match_dup 0) (zero_extend:HI (match_dup 2)))])] + { + operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); + }) + (define_insn "*zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] |