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author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-08-30 11:10:36 +0000 |
---|---|---|
committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-08-30 11:10:36 +0000 |
commit | 304b9962830476dce3fe7632713e5f5ce002c050 (patch) | |
tree | 4357020c2fa6f4639a809965e72c48c49d2ceb7c /gcc/config | |
parent | fffbab82e7fd15ef695159746a0ce7b9ac906778 (diff) | |
download | gcc-304b9962830476dce3fe7632713e5f5ce002c050.zip gcc-304b9962830476dce3fe7632713e5f5ce002c050.tar.gz gcc-304b9962830476dce3fe7632713e5f5ce002c050.tar.bz2 |
[18/77] Make int_mode_for_mode return an opt_scalar_int_mode
Also use int_mode_for_mode instead of (int_)mode_for_size
in cases where the requested size was the bitsize of an
existing mode.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* machmode.h (opt_mode::else_blk): New function.
(int_mode_for_mode): Declare.
* stor-layout.c (int_mode_for_mode): Return an opt_scalar_int_mode.
* builtins.c (expand_builtin_signbit): Adjust for new int_mode_for_mode
return type.
* cfgexpand.c (expand_debug_expr): Likewise.
* combine.c (gen_lowpart_or_truncate): Likewise.
(gen_lowpart_for_combine): Likewise.
* config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Likewise.
* config/avr/avr.c (avr_to_int_mode): Likewise.
(avr_out_plus_1): Likewise.
(avr_out_plus): Likewise.
(avr_out_round): Likewise.
* config/i386/i386.c (ix86_split_to_parts): Likewise.
* config/s390/s390.c (s390_expand_vec_compare_cc): Likewise.
(s390_expand_vcond): Likewise.
* config/spu/spu.c (spu_split_immediate): Likewise.
(spu_expand_mov): Likewise.
* dse.c (get_stored_val): Likewise.
* expmed.c (store_bit_field_1): Likewise.
(convert_extracted_bit_field): Use int_mode_for_mode instead of
int_mode_for_size.
(extract_bit_field_1): Adjust for new int_mode_for_mode return type.
(extract_low_bits): Likewise.
* expr.c (emit_group_load_1): Likewise. Separate out the BLKmode
handling rather than repeating the check.
(emit_group_store): Likewise.
(emit_move_via_integer): Adjust for new int_mode_for_mode return type.
* optabs.c (expand_absneg_bit): Likewise.
(expand_copysign_absneg): Likewise.
(expand_copysign_bit): Likewise.
* tree-if-conv.c (ifcvt_can_use_mask_load_store): Likewise.
* tree-vect-slp.c (vect_transform_slp_perm_load): Likewise.
* tree-vect-stmts.c (vect_gen_perm_mask_any): Likewise.
* var-tracking.c (prepare_call_arguments): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_do_expand_vec_perm): Use
int_mode_for_mode instead of mode_for_size.
* config/rs6000/rs6000.c (rs6000_do_expand_vec_perm): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251470
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/aarch64/aarch64.c | 13 | ||||
-rw-r--r-- | gcc/config/avr/avr.c | 8 | ||||
-rw-r--r-- | gcc/config/i386/i386.c | 2 | ||||
-rw-r--r-- | gcc/config/powerpcspe/powerpcspe.c | 6 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.c | 6 | ||||
-rw-r--r-- | gcc/config/s390/s390.c | 11 | ||||
-rw-r--r-- | gcc/config/spu/spu.c | 8 |
7 files changed, 26 insertions, 28 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3790830..54c30a2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4760,7 +4760,9 @@ aarch64_float_const_rtx_p (rtx x) && SCALAR_FLOAT_MODE_P (mode) && aarch64_reinterpret_float_as_int (x, &ival)) { - machine_mode imode = mode == HFmode ? SImode : int_mode_for_mode (mode); + machine_mode imode = (mode == HFmode + ? SImode + : int_mode_for_mode (mode).require ()); int num_instr = aarch64_internal_mov_immediate (NULL_RTX, gen_int_mode (ival, imode), false, imode); return num_instr < 3; @@ -4802,7 +4804,7 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode) if (aarch64_float_const_zero_rtx_p (x)) return true; - imode = int_mode_for_mode (mode); + imode = int_mode_for_mode (mode).require (); } else if (GET_CODE (x) == CONST_INT && SCALAR_INT_MODE_P (mode)) @@ -6978,8 +6980,9 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED, bool succeed = aarch64_reinterpret_float_as_int (x, &ival); gcc_assert (succeed); - machine_mode imode = mode == HFmode ? SImode - : int_mode_for_mode (mode); + machine_mode imode = (mode == HFmode + ? SImode + : int_mode_for_mode (mode).require ()); int ncost = aarch64_internal_mov_immediate (NULL_RTX, gen_int_mode (ival, imode), false, imode); *cost += COSTS_N_INSNS (ncost); @@ -8265,7 +8268,7 @@ aarch64_emit_approx_sqrt (rtx dst, rtx src, bool recp) } machine_mode mmsk - = mode_for_vector (int_mode_for_mode (GET_MODE_INNER (mode)), + = mode_for_vector (int_mode_for_mode (GET_MODE_INNER (mode)).require (), GET_MODE_NUNITS (mode)); if (!recp) { diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index 0f91e79..d3d6936 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -285,7 +285,7 @@ avr_to_int_mode (rtx x) return VOIDmode == mode ? x - : simplify_gen_subreg (int_mode_for_mode (mode), x, mode, 0); + : simplify_gen_subreg (int_mode_for_mode (mode).require (), x, mode, 0); } namespace { @@ -7739,7 +7739,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, machine_mode mode = GET_MODE (xop[0]); /* INT_MODE of the same size. */ - machine_mode imode = int_mode_for_mode (mode); + scalar_int_mode imode = int_mode_for_mode (mode).require (); /* Number of bytes to operate on. */ int n_bytes = GET_MODE_SIZE (mode); @@ -8242,7 +8242,7 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) rtx xpattern = INSN_P (insn) ? single_set (as_a <rtx_insn *> (insn)) : insn; rtx xdest = SET_DEST (xpattern); machine_mode mode = GET_MODE (xdest); - machine_mode imode = int_mode_for_mode (mode); + scalar_int_mode imode = int_mode_for_mode (mode).require (); int n_bytes = GET_MODE_SIZE (mode); enum rtx_code code_sat = GET_CODE (SET_SRC (xpattern)); enum rtx_code code @@ -9177,7 +9177,7 @@ const char* avr_out_round (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *xop, int *plen) { machine_mode mode = GET_MODE (xop[0]); - machine_mode imode = int_mode_for_mode (mode); + scalar_int_mode imode = int_mode_for_mode (mode).require (); // The smallest fractional bit not cleared by the rounding is 2^(-RP). int fbit = (int) GET_MODE_FBIT (mode); double_int i_add = double_int_zero.set_bit (fbit-1 - INTVAL (xop[2])); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 88850bd..c574c95 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -26361,7 +26361,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, machine_mode mode) if (GET_CODE (operand) == CONST_VECTOR) { - machine_mode imode = int_mode_for_mode (mode); + scalar_int_mode imode = int_mode_for_mode (mode).require (); /* Caution: if we looked through a constant pool memory above, the operand may actually have a different mode now. That's ok, since we want to pun this all the way back to an integer. */ diff --git a/gcc/config/powerpcspe/powerpcspe.c b/gcc/config/powerpcspe/powerpcspe.c index c4ddf40..5fdba02 100644 --- a/gcc/config/powerpcspe/powerpcspe.c +++ b/gcc/config/powerpcspe/powerpcspe.c @@ -38664,10 +38664,8 @@ rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1, imode = vmode; if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT) - { - imode = mode_for_size (GET_MODE_UNIT_BITSIZE (vmode), MODE_INT, 0); - imode = mode_for_vector (imode, nelt); - } + imode = mode_for_vector + (int_mode_for_mode (GET_MODE_INNER (vmode)).require (), nelt); x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm)); x = expand_vec_perm (vmode, op0, op1, x, target); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5086a7a..9a0b42a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -35507,10 +35507,8 @@ rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1, imode = vmode; if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT) - { - imode = mode_for_size (GET_MODE_UNIT_BITSIZE (vmode), MODE_INT, 0); - imode = mode_for_vector (imode, nelt); - } + imode = mode_for_vector + (int_mode_for_mode (GET_MODE_INNER (vmode)).require (), nelt); x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm)); x = expand_vec_perm (vmode, op0, op1, x, target); diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index a3b7418..b5c0bd1 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -6466,9 +6466,9 @@ s390_expand_vec_compare_cc (rtx target, enum rtx_code code, case LE: cc_producer_mode = CCVFHEmode; code = GE; swap_p = true; break; default: gcc_unreachable (); } - scratch_mode = mode_for_vector ( - int_mode_for_mode (GET_MODE_INNER (GET_MODE (cmp1))), - GET_MODE_NUNITS (GET_MODE (cmp1))); + scratch_mode = mode_for_vector + (int_mode_for_mode (GET_MODE_INNER (GET_MODE (cmp1))).require (), + GET_MODE_NUNITS (GET_MODE (cmp1))); gcc_assert (scratch_mode != BLKmode); if (inv_p) @@ -6575,8 +6575,9 @@ s390_expand_vcond (rtx target, rtx then, rtx els, /* We always use an integral type vector to hold the comparison result. */ - result_mode = mode_for_vector (int_mode_for_mode (GET_MODE_INNER (cmp_mode)), - GET_MODE_NUNITS (cmp_mode)); + result_mode = mode_for_vector + (int_mode_for_mode (GET_MODE_INNER (cmp_mode)).require (), + GET_MODE_NUNITS (cmp_mode)); result_target = gen_reg_rtx (result_mode); /* We allow vector immediates as comparison operands that diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index 7216937..dfa777e 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -1493,10 +1493,9 @@ spu_split_immediate (rtx * ops) unsigned char arrlo[16]; rtx to, temp, hi, lo; int i; - machine_mode imode = mode; /* We need to do reals as ints because the constant used in the IOR might not be a legitimate real constant. */ - imode = int_mode_for_mode (mode); + scalar_int_mode imode = int_mode_for_mode (mode).require (); constant_to_array (mode, ops[1], arrhi); if (imode != mode) to = simplify_gen_subreg (imode, ops[0], mode, 0); @@ -1522,10 +1521,9 @@ spu_split_immediate (rtx * ops) unsigned char arr_andbi[16]; rtx to, reg_fsmbi, reg_and; int i; - machine_mode imode = mode; /* We need to do reals as ints because the constant used in the * AND might not be a legitimate real constant. */ - imode = int_mode_for_mode (mode); + scalar_int_mode imode = int_mode_for_mode (mode).require (); constant_to_array (mode, ops[1], arr_fsmbi); if (imode != mode) to = simplify_gen_subreg(imode, ops[0], GET_MODE (ops[0]), 0); @@ -4430,7 +4428,7 @@ spu_expand_mov (rtx * ops, machine_mode mode) if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1])) { rtx from = SUBREG_REG (ops[1]); - machine_mode imode = int_mode_for_mode (GET_MODE (from)); + scalar_int_mode imode = int_mode_for_mode (GET_MODE (from)).require (); gcc_assert (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_CLASS (imode) == MODE_INT |